參數(shù)資料
型號(hào): TLV320AIC3106_0706
廠商: Texas Instruments, Inc.
元件分類: Codec
英文描述: LOW-POWER STEREO AUDIO CODEC FOR PORTABLE AUDIO/TELEPHONY
中文描述: 低功耗立體聲音頻編解碼器的便攜式音頻/電話
文件頁(yè)數(shù): 57/102頁(yè)
文件大?。?/td> 1259K
代理商: TLV320AIC3106_0706
www.ti.com
TLV320AIC3106
SLAS509B–DECEMBER 2006–REVISED JUNE 2007
Page 0 / Register 25:
MICBIAS Control Register
BIT
READ/
WRITE
R/W
RESET
VALUE
00
DESCRIPTION
D7–D6
MICBIAS Level Control
00: MICBIAS output is powered down
01: MICBIAS output is powered to 2.0V
10: MICBIAS output is powered to 2.5V
11: MICBIAS output is connected to AVDD
Digital Microphone Control
00: If Digital MIC is enabled, both Left and Right Digital MICs are available
01: If Digital MIC is enabled, Left Digital MIC and Right ADC are available
10: If Digital MIC is enabled, Left ADC and Right Digital MIC are available
11: Reserved. Don’t write to this sequence.
Reserved. Don’t write to this register bit.
Reserved. Write only zeros to these register bits.
D5–D4
R/W
00
D3
R
R
0
D2–D0
XXX
Page 0 / Register 26:
Left AGC Control Register A
BIT
READ/
WRITE
R/W
RESET
VALUE
0
DESCRIPTION
D7
Left AGC Enable
0: Left AGC is disabled
1: Left AGC is enabled
Left AGC Target Level
000: Left AGC target level = –5.5-dB
001: Left AGC target level = –8-dB
010: Left AGC target level = –10-dB
011: Left AGC target level = –12-dB
100: Left AGC target level = –14-dB
101: Left AGC target level = –17-dB
110: Left AGC target level = –20-dB
111: Left AGC target level = –24-dB
Left AGC Attack Time
These time constants
(1)
will not be accurate when double rate audio mode is enabled.
00: Left AGC attack time = 8-msec
01: Left AGC attack time = 11-msec
10: Left AGC attack time = 16-msec
11: Left AGC attack time = 20-msec
Left AGC Decay Time
These time constants
(1)
will not be accurate when double rate audio mode is enabled.
00: Left AGC decay time = 100-msec
01: Left AGC decay time = 200-msec
10: Left AGC decay time = 400-msec
11: Left AGC decay time = 500-msec
D6–D4
R/W
000
D3–D2
R/W
00
D1–D0
R/W
00
(1)
Time constants are valid when DRA is not enabled. The values would change if DRA is enabled.
Page 0 / Register 27:
Left AGC Control Register B
BIT
READ/
WRITE
R/W
RESET
VALUE
1111111
DESCRIPTION
D7-D1
Left AGC Maximum Gain Allowed
0000000: Maximum gain = 0.0-dB
0000001: Maximum gain = 0.5-dB
0000010: Maximum gain = 1.0-dB
1110110: Maximum gain = 59.0-dB
1110111–111111: Maximum gain = 59.5-dB
Reserved. Write only zero to this register bit.
D0
R/W
0
57
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