參數(shù)資料
型號: TLV320AIC3106_0706
廠商: Texas Instruments, Inc.
元件分類: Codec
英文描述: LOW-POWER STEREO AUDIO CODEC FOR PORTABLE AUDIO/TELEPHONY
中文描述: 低功耗立體聲音頻編解碼器的便攜式音頻/電話
文件頁數(shù): 26/102頁
文件大?。?/td> 1259K
代理商: TLV320AIC3106_0706
www.ti.com
N-1
N-2
1
0
N-1
N-2
1
0
word
clock
bitclock
data
in/out
Right Channel Data
Right Channel Data
Left Channel Data
Left Channel Data
N-1
N-2
1
0
N-1
N-2
1
0
word
clock
bitclock
data
in/out
DSP Mode
Left Justified Mode
offset
offset
offset
AUDIO DATA CONVERTERS
The TLV320AIC3106 supports the following standard audio sampling rates: 8 kHz, 11.025 kHz, 12 kHz, 16 kHz,
22.05 kHz, 24 kHz, 32 kHz, 44.1 kHz, 48 kHz, 88.2 kHz, and 96 kHz. The converters can also operate at
different sampling rates in various combinations, which are described further below.
AUDIO CLOCK GENERATION
The audio converters in the TLV320AIC3106 need an internal audio master clock at a frequency of 256
×
Fsref,
which can be obtained in a variety of manners from an external clock signal applied to the device.
TLV320AIC3106
SLAS509B–DECEMBER 2006–REVISED JUNE 2007
Figure 24. DSP Mode and Left Justified Modes, Showing the
Effect of a Programmed Data Word Offset
The data converters are based on the concept of an Fsref rate that is used internal to the part, and it is related
to the actual sampling rates of the converters through a series of ratios. For typical sampling rates, Fsref will be
either 44.1 kHz or 48 kHz, although it can realistically be set over a wider range of rates up to 53 kHz, with
additional restrictions applying if the PLL is used. This concept is used to set the sampling rates of the ADC and
DAC, and also to enable high quality playback of low sampling rate data, without high frequency audible noise
being generated.
The sampling rate of the ADC and DAC can be set to Fsref/NDAC or 2
×
Fsref/NDAC, with NDAC being 1, 1.5, 2,
2.5, 3, 3.5, 4, 4.5, 5, 5.5, or 6.
While only one Fsref can be used at a time in the part, the ADC and DAC sampling rates can differ from each
other by using different NADC and NDAC divider ratios for each. For example, with Fsref=44.1-kHz, the DAC
sampling rate can be set to 44.1-kHz by using NDAC=1, while the ADC sampling rate can be set to 8.018-kHz
by using NADC=5.5.
When the ADCs and DACs are operating at different sampling rates, an additional word clock is required, to
provide information regarding where data begins for the ADC versus the DAC. In this case, the standard bit
clock signal (which can be supplied through the BCLK pin or through GPIO2) is used to transfer both ADC and
DAC data, the standard word clock signal is used to identify the start of the DAC data, and a separate ADC
word clock signal (denoted ADWK) is used. This clock can be supplied or generated from GPIO1 at the same
time the DAC word clock is supplied or generated from WCLK.
A more detailed diagram of the audio clock section of the TLV320AIC3106 is shown in
Figure 25
.
26
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TLV320AIC3106EVM 功能描述:音頻 IC 開發(fā)工具 TLV320AIC3106 Eval Mod RoHS:否 制造商:Texas Instruments 產(chǎn)品:Evaluation Kits 類型:Audio Amplifiers 工具用于評估:TAS5614L 工作電源電壓:12 V to 38 V
TLV320AIC3106EVM-K 功能描述:音頻 IC 開發(fā)工具 TLV320AIC3106EVM-K Eval Mod RoHS:否 制造商:Texas Instruments 產(chǎn)品:Evaluation Kits 類型:Audio Amplifiers 工具用于評估:TAS5614L 工作電源電壓:12 V to 38 V
TLV320AIC3106IGQE 制造商:Texas Instruments 功能描述:AUD CODEC 2ADC / 2DAC 24BIT 80BGA - Trays
TLV320AIC3106IGQER 制造商:Texas Instruments 功能描述:AUD CODEC 2ADC / 2DAC 24BIT 80BGA - Tape and Reel
TLV320AIC3106IRGZR 功能描述:接口—CODEC Lo-Pwr Stereo CODEC RoHS:否 制造商:Texas Instruments 類型: 分辨率: 轉(zhuǎn)換速率:48 kSPs 接口類型:I2C ADC 數(shù)量:2 DAC 數(shù)量:4 工作電源電壓:1.8 V, 2.1 V, 2.3 V to 5.5 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:DSBGA-81 封裝:Reel