- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄383878 > TAS5028APAG (Texas Instruments, Inc.) 8 Channel Digital Audio PWM Processor PDF資料下載
參數(shù)資料
| 型號(hào)： | TAS5028APAG |
| 廠商： | Texas Instruments, Inc. |
| 英文描述： | 8 Channel Digital Audio PWM Processor |
| 中文描述： | 8通道數(shù)字音頻PWM處理器 |
| 文件頁數(shù)： | 53/82頁 |
| 文件大?。?/td> | 1226K |
| 代理商： | TAS5028APAG |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁第31頁第32頁第33頁第34頁第35頁第36頁第37頁第38頁第39頁第40頁第41頁第42頁第43頁第44頁第45頁第46頁第47頁第48頁第49頁第50頁第51頁第52頁當(dāng)前第53頁第54頁第55頁第56頁第57頁第58頁第59頁第60頁第61頁第62頁第63頁第64頁第65頁第66頁第67頁第68頁第69頁第70頁第71頁第72頁第73頁第74頁第75頁第76頁第77頁第78頁第79頁第80頁第81頁第82頁
I
2
C Serial Control Interface (Slave Address 0x36)
46
SLES120
September 2004
TAS5028A
Supplying a subaddress for each subaddress transaction is referred to as random I
2
C addressing. The
TAS5028A also supports sequential I
2
C addressing. For write transactions, if a subaddress is issued followed
by data for that subaddress and the fifteen subaddresses that follow, a sequential I
2
C write transaction has
taken place, and the data for all 16 subaddresses is successfully received by the TAS5028A. For I
2
C
sequential write transactions, the subaddress then serves as the start address and the amount of data
subsequently transmitted, before a stop or start is transmitted, determines how many subaddresses are
written. As was true for random addressing, sequential addressing requires that a complete set of data be
transmitted. If only a partial set of data is written to the last subaddress, the data for the last subaddress is
discarded. However, all other data written is accepted; just the incomplete data is discarded.
Single
Byte Write
4.3
As shown in Figure 4
2, a single
byte data write transfer begins with the master device transmitting a start
condition followed by the I
2
C device address and the read/write bit. The read/write bit determines the direction
of the data transfer. For a write data transfer, the read/write bit will be a 0. After receiving the correct I
2
C device
address and the read/write bit, the TAS5028A device responds with an acknowledge bit. Next, the master
transmits the address byte or bytes corresponding to the TAS5028A internal memory address being
accessed. After receiving the address byte, the TAS5028A again responds with an acknowledge bit. Next, the
master device transmits the data byte to be written to the memory address being accessed. After receiving
the data byte, the TAS5028A again responds with an acknowledge bit. Finally, the master device transmits
a stop condition to complete the single
byte data
write transfer.
A6
A5
A4
A3
A2
A1
A0
R/W ACK
A7
A6
A5
A4
A3
A2
A1
A0
ACK
D7
D6
D5
D4
D3
D2
D1
D0
ACK
Start
Condition
Stop
Condition
Acknowledge
Acknowledge
Acknowledge
I
2
C Device Address and
Read/Write Bit
Sub-Address
Data Byte
Figure 4
2. Single
Byte Write Transfer
4.4
Multiple
Byte Write
A multiple
byte data write transfer is identical to a single
byte data write transfer except that multiple data
bytes are transmitted by the master device to TAS5028A as shown in Figure 4
3. After receiving each data
byte, the TAS5028A responds with an acknowledge bit.
D7
D0 ACK
Stop
Condition
Acknowledge
I
2
C Device Address and
Read/Write Bit
Sub-Address
Last Data Byte
A6
A5
A1
A0
R/W ACK
A7
A5
A1
A0
ACK
D7
ACK
Start
Condition
Acknowledge
Acknowledge
Acknowledge
First Data Byte
A4
A3
A6
Other Data Bytes
ACK
Acknowledge
D0
D7
D0
Figure 4
3. Multiple
Byte Write Transfer
4.5
Incremental Multiple
Byte Write
The I
2
C supports a special mode which permits I
2
C write operations to be broken up into multiple data write
operations that are multiples of 4 data bytes. These are 6
byte, 10
byte, 14
byte, 18
byte, ... etc., write
operations that are composed of a device address, read/write bit, and subaddress and any multiple of 4 bytes
of data. This permits the system to incrementally write large register values without blocking other I
2
C
transactions.
This feature is enabled by the append subaddress function in the TAS5028A. This function enables the
TAS5028A to append 4 bytes of data to a register that was opened by a previous I
2
C register write operation
but has not received its complete number of data bytes. Because the length of the long registers is a multiple
of 4 bytes, using 4-byte transfers has only an integer number of append operations.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| TAS5028APAGG4 | 8 Channel Digital Audio PWM Processor |
| TAS5028APAGR | 8 Channel Digital Audio PWM Processor |
| TAS5028APAGRG4 | 8 Channel Digital Audio PWM Processor |
| TAS5028PAGR | 8 Channel Digital Audio PWM Processor |
| TAS5028PAGRG4 | 8 Channel Digital Audio PWM Processor |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| TAS5028APAGG4 | 功能描述:音頻放大器 8Ch Dig Aud PWM Proc RoHS:否 制造商:STMicroelectronics 產(chǎn)品:General Purpose Audio Amplifiers 輸出類型:Digital 輸出功率: THD + 噪聲: 工作電源電壓:3.3 V 電源電流: 最大功率耗散: 最大工作溫度: 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:TQFP-64 封裝:Reel |
| TAS5028APAGR | 功能描述:音頻放大器 8Ch Dig Aud PWM Proc RoHS:否 制造商:STMicroelectronics 產(chǎn)品:General Purpose Audio Amplifiers 輸出類型:Digital 輸出功率: THD + 噪聲: 工作電源電壓:3.3 V 電源電流: 最大功率耗散: 最大工作溫度: 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:TQFP-64 封裝:Reel |
| TAS5028APAGRG4 | 功能描述:音頻放大器 8Ch Dig Aud PWM Proc RoHS:否 制造商:STMicroelectronics 產(chǎn)品:General Purpose Audio Amplifiers 輸出類型:Digital 輸出功率: THD + 噪聲: 工作電源電壓:3.3 V 電源電流: 最大功率耗散: 最大工作溫度: 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:TQFP-64 封裝:Reel |
| TAS5028PAG | 功能描述:音頻 DSP 8 Ch Digital Audio PWM Processor RoHS:否 制造商:Texas Instruments 工作電源電壓: 電源電流: 工作溫度范圍: 安裝風(fēng)格: 封裝 / 箱體: 封裝:Tube |
| TAS5028PAGG4 | 功能描述:音頻 DSP 8 Ch Digital Audio PWM Processor RoHS:否 制造商:Texas Instruments 工作電源電壓: 電源電流: 工作溫度范圍: 安裝風(fēng)格: 封裝 / 箱體: 封裝:Tube |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。