參數(shù)資料
型號(hào): TAS5028APAG
廠商: Texas Instruments, Inc.
英文描述: 8 Channel Digital Audio PWM Processor
中文描述: 8通道數(shù)字音頻PWM處理器
文件頁(yè)數(shù): 46/82頁(yè)
文件大小: 1226K
代理商: TAS5028APAG
Electrical Specifications
39
SLES120
September 2004
TAS5028A
3.6.4 Reset Timing (RESET)
3.6.4.1
Control Signal Parameters Over Recommended Operating Conditions (Unless
Otherwise Noted)
PARAMETER
Time to M-STATE low
Pulse duration, RESET active
Time to enable I
2
C
Device startup time
MIN
TYP
MAX
370
None
UNITS
ns
ns
ms
ms
t
r(DMSTATE)
t
w(RESET)
t
r(I2C_ready)
t
r(run)
400
3
10
t
w(RESET)
Earliest time
that M-State
could be exited
RESET
M-State
t
r(DMSTATE)
= ~ < 300 ns
t
r(I2C_ready)
Start system
t
r(run)
Determine SCLK rate
and MCLK ratio Enable I
2
C
Figure 3
4. Reset Timing
Since a crystal time base is used, the system determines the CLK rates. Once the data rate and master clock
ratio is determined, the system outputs audio if a master volume command is issued.
3.6.5 Power-Down (PDN) Timing
3.6.5.1
Control Signal Parameters Over Recommended Operating Conditions (Unless Otherwise
Noted)
PARAMETER
MIN
TYP
MAX
300
UNITS
μ
s
t
p(DMSTATE)
Time to M-STATE low
Number of MCLKs preceding the release of PDN
Device startup time
5
t
su
120
ms
PDN
M-State
t
su
t
p(DMSTATE)
= ~ < 300
μ
s
Figure 3
5. Power-Down Timing
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TAS5028PAGG4 功能描述:音頻 DSP 8 Ch Digital Audio PWM Processor RoHS:否 制造商:Texas Instruments 工作電源電壓: 電源電流: 工作溫度范圍: 安裝風(fēng)格: 封裝 / 箱體: 封裝:Tube