參數(shù)資料
型號(hào): TAS5028APAG
廠商: Texas Instruments, Inc.
英文描述: 8 Channel Digital Audio PWM Processor
中文描述: 8通道數(shù)字音頻PWM處理器
文件頁(yè)數(shù): 34/82頁(yè)
文件大?。?/td> 1226K
代理商: TAS5028APAG
TAS5028A Controls and Status
27
SLES112 — June 2004
TAS5028A
After the initialization time, the TAS5028A starts the transition to the operational state with the Master volume
set at mute.
Because the TAS5028A has an external crystal time base, following the release of RESET, the TAS5028A sets
the MCLK and data rates and perform the initialization sequences. The PWM outputs are held at a mute state
until the master volume is set to a value other than mute via I
2
C.
2.2.2 Power Down (PDN)
TheTAS5028A can be placed into the power down mode by holding the PDN terminal low. When power down
mode is entered, both the PLL and the oscillator are shut down. Volume is immediately set to full attenuation
(there is no ramp down). This control uses the PWM mute sequence that provides a low click and pop transition
to the hard mute state (M). A detailed description of the PWM mute sequence is contained in the PWM section.
Power down is an asynchronous operation that does not require MCLK to go into the power down state. To
initiate the power-up sequence requires MCLK to be operational and the TAS5028A to receive 5 MCLKs prior
to the release of PDN.
As long as the PDN terminal is held low the device is in the power down state with the PWM outputs in a hard
mute (M) state. During power down, all I
2
C and serial data bus operations are ignored. Table 2
3 shows the
device output signals while PDN is active.
Table 2
3. Device Outputs During Power Down
SIGNAL
Valid
PWM P-outputs
PWM M-outputs
SDA
SIGNAL STATE
Low
M-state = low
M-state = low
Signal input
Following the application of PDN, the TAS5028A does not perform a quiet shutdown to prevent clicks and pops
produced during the application (the leading edge) of this command. The application of PDN immediately
performs a PWM stop. A quiet stop sequence can be performed by first applying MUTE before PDN.
When PDN is released, the system goes to the end state specified by MUTE and BKND_ERR pins and the
I
2
C register settings.
The crystal time base allows the TAS5028A to determine the CLK rates. Once these rates are determined,
the TAS5028A unmutes the audio.
2.2.3 Backend Error (BKND_ERR)
Backend error is used to provide error management for backend error conditions. Backend error is a level
sensitive signal. Backend error can be initiated by bringing the BKND_ERR terminal low for a minimum 5
MCLK cycles. When BKND_ERR is brought low, the PWM sets either six or eight channels into the PWM
backend error state. This state is described in the PWM section. Once the backend error sequence is initiated,
a delay of 5 ms is performed before the system starts the output re
initialization sequence. After the
initialization time, the TAS5028A begins normal operation. Backend error does not affect other PWM
modulator operations
The number of channels that are affected by the BKND_ERR signal is dependent upon the 6-channel
configuration signal. If the I
2
C setting 6-channel configuration is false, the TAS5028A places all eight PWM
outputs in the PWM backend error state, while not affecting any other internal settings or operations. If the
I
2
C setting six configuration is true, the TAS5028A brings the PWM outputs 1
6 to a backend error state, while
not affecting any other internal settings or operations. Table 2
4 shows the device output signal states during
backend error.
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