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參數(shù)資料
| 型號(hào)： | TAS5028APAG |
| 廠商： | Texas Instruments, Inc. |
| 英文描述： | 8 Channel Digital Audio PWM Processor |
| 中文描述： | 8通道數(shù)字音頻PWM處理器 |
| 文件頁數(shù)： | 39/82頁 |
| 文件大?。?/td> | 1226K |
| 代理商： | TAS5028APAG |
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TAS5028A Controls and Status
32
SLES112 — June 2004
TAS5028A
This delay is generated in the PWM and can be changed at any time through the serial control interface I
2
C
registers 0x1B – 0x22. The absolute offset for channel 1 is set in I
2
C sub-address 0x23.
NOTE:
If used correctly, setting the PWM channel delay can optimize the performance of a
pure path digital amplifier system. The setting is based upon the type of backend power device
that is used and the layout. These values are set during initialization using the I
2
C serial
interface. Unless otherwise noted, use the default values given in Table 2
9.
Master Clock and Serial Data Rate Controls
2.4
The TAS5028A function only as a receiver of the MCLK (master clock), SCLK (shift clock), and LRCLK
(left/right clock) signals that controls the flow of data on the four serial data interfaces. The 13.5-MHz external
crystal allows the TAS5028A to automatically detect MCLK and the data rate.
The MCLK frequency can be 64 x Fs, 128 x Fs, 196 x Fs, 256 x Fs, 384 x Fs, 512 x Fs, or 768 x Fs.
The TAS5028A operates with the serial data interface signals LRCLK and SCLK synchronized to MCLK.
However, there is no constraint as to the phase relationship of these signals. The TAS5028A accepts a 64 x
Fs SCLK rate and a 1 x Fs LRCLK.
If the phase of SCLK or LRCLK drifts more than
±
10 MCLK cycles since the last RESET, the TAS5028A
performs a clock error and resynchronize the clock timing.
The clock and serial data interface have several control parameters:
MCLK ratio 64 Fs, 128 Fs, 196 Fs, 256 Fs, 384 Fs, 512 Fs, or 768 Fs)
I
2
C parameter
Data rate 32, 38, 44.1,48, 88.2, 96, 176.4, 192 kHz
I
2
C parameter
AM mode enable / disable
I
2
C parameter
During AM interference avoidance, the clock control circuitry utilizes three other configuration inputs:
Tuned AM frequency (for AM interference avoidance) (550
1750 kHz)
I
2
C parameter
Frequency set select (1
4)
I
2
C parameter
Sample rate
I
2
C parameter or auto detected
2.4.1 PLL Operation
The TAS5028A uses two internal clocks generated by two internal phase-locked loops (PLLs), the digital PLL
(DPLL) and the analog PLL (APLL). The analog PLL provides the reference clock for the PWM. The digital
PLL provides the reference clock for the digital audio processor and the control logic.
The master clock MCLK input provides the input reference clock for the APLL. The external 13.5-MHz crystal
provides the input reference clock for the digital PLL. The crystal provides a time base to support a number
of operations, including the detection of the MCLK ratio, the data rate, and clock error conditions. The crystal
time base provides a constant rate for all controls and signal timing.
Even if MCLK is not present, the TAS5028A can receive and store I
2
C commands and provide status.
Bank Controls
2.5
The TAS5028A permits the user to specify and assign sample rate dependent parameters for Tone in one of
three banks that can be manually selected or selected automatically based upon the data sample rate. Each
bank can be enabled for one or more specific sample rates via I
2
C bank control register 0x40. Each bank set
holds the following values:
Five bass filter-set selections (register 0xDA)
Five treble filter-set selections (register 0xDC)
The default selection for bank control is manual bank with bank 1 selected. Note that if bank switching is used,
bank 2 and bank 3 must be programmed on power
up since the default values are all zeroes. If bank switching
is used and bank 2 and bank 3 are not programmed correctly, then the output of the TAS5028A could be muted
when switching to those banks.
相關(guān)PDF資料 |
PDF描述 |
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| TAS5028APAGG4 | 8 Channel Digital Audio PWM Processor |
| TAS5028APAGR | 8 Channel Digital Audio PWM Processor |
| TAS5028APAGRG4 | 8 Channel Digital Audio PWM Processor |
| TAS5028PAGR | 8 Channel Digital Audio PWM Processor |
| TAS5028PAGRG4 | 8 Channel Digital Audio PWM Processor |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| TAS5028APAGG4 | 功能描述:音頻放大器 8Ch Dig Aud PWM Proc RoHS:否 制造商:STMicroelectronics 產(chǎn)品:General Purpose Audio Amplifiers 輸出類型:Digital 輸出功率: THD + 噪聲: 工作電源電壓:3.3 V 電源電流: 最大功率耗散: 最大工作溫度: 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:TQFP-64 封裝:Reel |
| TAS5028APAGR | 功能描述:音頻放大器 8Ch Dig Aud PWM Proc RoHS:否 制造商:STMicroelectronics 產(chǎn)品:General Purpose Audio Amplifiers 輸出類型:Digital 輸出功率: THD + 噪聲: 工作電源電壓:3.3 V 電源電流: 最大功率耗散: 最大工作溫度: 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:TQFP-64 封裝:Reel |
| TAS5028APAGRG4 | 功能描述:音頻放大器 8Ch Dig Aud PWM Proc RoHS:否 制造商:STMicroelectronics 產(chǎn)品:General Purpose Audio Amplifiers 輸出類型:Digital 輸出功率: THD + 噪聲: 工作電源電壓:3.3 V 電源電流: 最大功率耗散: 最大工作溫度: 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:TQFP-64 封裝:Reel |
| TAS5028PAG | 功能描述:音頻 DSP 8 Ch Digital Audio PWM Processor RoHS:否 制造商:Texas Instruments 工作電源電壓: 電源電流: 工作溫度范圍: 安裝風(fēng)格: 封裝 / 箱體: 封裝:Tube |
| TAS5028PAGG4 | 功能描述:音頻 DSP 8 Ch Digital Audio PWM Processor RoHS:否 制造商:Texas Instruments 工作電源電壓: 電源電流: 工作溫度范圍: 安裝風(fēng)格: 封裝 / 箱體: 封裝:Tube |
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