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參數(shù)資料
| 型號(hào)： | SY89538L |
| 廠商： | Micrel Semiconductor,Inc. |
| 英文描述： | 3.3V PRECISION LVPECL AND LVDS PROGRAMMABLE MULTIPLE OUTPUT BANK CLOCK SYNTHESIZER AND FANOUT BUFFER WITH ZERO DELAY |
| 中文描述： | 3.3精密LVPECL和LVDS可編程多個(gè)OUTPUT銀行時(shí)鐘合成器與扇出緩沖器與零延遲 |
| 文件頁數(shù)： | 6/23頁 |
| 文件大?。?/td> | 628K |
| 代理商： | SY89538L |
Micrel, Inc.
Pin Description
Input/Output
SY89538L
October 2005
M9999-101105-B
hbwhelp@micrel.com
or (408) 955-1690
6
Pin Number
Pin Name
Pin Function
3, 4
FBIN, /FBIN
External Feedback Input used as the zero delay input. Output feeds into the inputs to
configure the device in zero-delay mode, which forces the output frequency to the
same frequency of the RFCK frequency. Requires external termination. See “Zero
Delay FBIN Input” section for more details.
8, 9
RFCK, /RFCK
Reference Clock Differential Input. Input accepts any input, single-ended or
differential: TTL/CMOS, LVPECL, LVDS, HSTL, and SSTL. RFCK requires an
external termination. See “Input Interface” and “Input Termination” sections for more
details.
11, 12
XTAL2, XTAL1
Crystal Input. Directly connect a series resonant crystal across inputs. See “Quartz
Crystal Oscillator Specification” table. Place crystal as close to the input as possible,
keep XTAL and traces away from adjacent noisy traces to minimize noise coupling,
and place the XTAL on the same side as the SY89538L (component side).
17, 18
20, 21
49, 50
52, 53
POUT0, /POUT0
POUT1, /POUT1
POUT2, /POUT2
POUT3, /POUT3
100K LVPECL Output Drivers. Terminate all LVPECL outputs with 50
to V
CCO
–2V.
Each output pair has a respective output frequency control (PSELx, PENx, DSEL).
See “LVPECL Output Post-Divider and Frequency Select Table” for proper decoding.
For low-jitter applications, unused LVPECL output pairs should be terminated with
pull-down resistors. See “Output Termination Recommendations” section for
termination detail.
38, 39
41, 42
44, 45
LOUT0, /LOUT0
LOUT1, /LOUT1
LOUT2, /LOUT2
Differential LVDS-Compatible Output Drivers. Output termination is 100
across the
pair. For low-jitter applications, unused LVDS output pairs should be terminated with
100
across the pair. See “Output Termination Recommendations” section for
details.
32, 48,
54, 61, 64
NC
No connect.
Input Driver Select Table
RSEL1
RSEL0
Internal Reference
Clock
Zero-Delay
MUX Divider
0
0
RFCK / 8
FBIN / 8
0
1
RFCK / 4
FBIN / 4
1
0
RFCK / 2
FBIN / 2
1
1
RFCK / 1
FBIN / 1
Table 1. Reference Input Divider and Zero-Delay MUX Divider Select Table
Pre-Divider Frequency Select Table
PDSEL1
PDSEL0
Pre-Div-Out Frequency
0
0
(VCO/2) / 5
0
1
(VCO/2) / 4
1
0
(VCO/2) / 3
1
1
(VCO/2) / 2
Table 2. Pre-Divider Select Table
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| SY89538L_06 | 制造商:MICREL 制造商全稱:Micrel Semiconductor 功能描述:3.3V, Precision LVPECL and LVDS Programmable Multiple Output Bank Clock Synthesizer and Fanout Buffer with Zero Delay |
| SY89538L_08 | 制造商:MICREL 制造商全稱:Micrel Semiconductor 功能描述:3.3V, Precision LVPECL and LVDS Programmable Multiple Output Bank Clock Synthesizer |
| SY89538LHG | 功能描述:IC SYNTH/BUFF LVPECL/LVDS 64TQFP RoHS:是 類別:集成電路 (IC) >> 時(shí)鐘/計(jì)時(shí) - 時(shí)鐘發(fā)生器，PLL，頻率合成器 系列:Precision Edge® 產(chǎn)品變化通告:Product Discontinuation 04/May/2011 標(biāo)準(zhǔn)包裝:96 系列:- 類型:時(shí)鐘倍頻器，零延遲緩沖器 PLL:帶旁路 輸入:LVTTL 輸出:LVTTL 電路數(shù):1 比率 - 輸入:輸出:1:8 差分 - 輸入:輸出:無/無 頻率 - 最大:133.3MHz 除法器/乘法器:是/無 電源電壓:3 V ~ 3.6 V 工作溫度:0°C ~ 70°C 安裝類型:表面貼裝 封裝/外殼:16-TSSOP（0.173"，4.40mm 寬） 供應(yīng)商設(shè)備封裝:16-TSSOP 包裝:管件 其它名稱:23S08-5HPGG |
| SY89538LHG TR | 功能描述:IC SYNTHESIZR LVPECL/LVDS 64TQFP RoHS:是 類別:集成電路 (IC) >> 時(shí)鐘/計(jì)時(shí) - 時(shí)鐘發(fā)生器，PLL，頻率合成器 系列:Precision Edge® 產(chǎn)品變化通告:Product Discontinuation 04/May/2011 標(biāo)準(zhǔn)包裝:96 系列:- 類型:時(shí)鐘倍頻器，零延遲緩沖器 PLL:帶旁路 輸入:LVTTL 輸出:LVTTL 電路數(shù):1 比率 - 輸入:輸出:1:8 差分 - 輸入:輸出:無/無 頻率 - 最大:133.3MHz 除法器/乘法器:是/無 電源電壓:3 V ~ 3.6 V 工作溫度:0°C ~ 70°C 安裝類型:表面貼裝 封裝/外殼:16-TSSOP（0.173"，4.40mm 寬） 供應(yīng)商設(shè)備封裝:16-TSSOP 包裝:管件 其它名稱:23S08-5HPGG |
| SY89538LHGTR | 制造商:MICREL 制造商全稱:Micrel Semiconductor 功能描述:3.3V PRECISION LVPECL AND LVDS PROGRAMMABLE MULTIPLE OUTPUT BANK CLOCK SYNTHESIZER AND FANOUT BUFFER WITH ZERO DELAY |
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