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參數(shù)資料
| 型號： | SY89538L |
| 廠商： | Micrel Semiconductor,Inc. |
| 英文描述： | 3.3V PRECISION LVPECL AND LVDS PROGRAMMABLE MULTIPLE OUTPUT BANK CLOCK SYNTHESIZER AND FANOUT BUFFER WITH ZERO DELAY |
| 中文描述： | 3.3精密LVPECL和LVDS可編程多個OUTPUT銀行時鐘合成器與扇出緩沖器與零延遲 |
| 文件頁數(shù)： | 16/23頁 |
| 文件大小： | 628K |
| 代理商： | SY89538L |
Micrel, Inc.
External Loop Filter Considerations
The SY89538L features an external PLL loop filter
that allows the users to tailor the PLL’s behavior. It is
recommended that ceramic capacitors with NPO or
X7R dielectric be used, since they have very low
effective series resistance. For applications that
require
ultra-low
cycle-to-cycle
components shown in Figure 4. Larger values of the
zero capacitor (capacitor shown in parallel) results in
less cycle-to- cycle jitter, however the total jitter
increases as the value of the zero capacitor
increases. In addition, as the zero capacitor
increases, loop stability decreases as the zero
capacitor begins to dominate over the pole capacitor
(capacitor in series with the damping resistor). The
external loop filter allows the user to change the loop
filter values for specific jitter requirements. Using a
smaller resistor in the loop filter decreases the PLL’s
loop bandwidth. This results in less noise from the
PLL input, but potentially more noise from the VCO.
Take care to keep the loop filter components on the
same side of the board and as close as possible to
the SY89538L’s LR and LF pins. To minimize noise
pick up on the loop filter pins, cut the ground plane
directly underneath the loop filter component pads
and traces. However, the benefit may not be
significant in all applications.
SY89538L
October 2005
M9999-101105-B
hbwhelp@micrel.com
or (408) 955-1690
16
jitter,
use
the
Figure 4. Loop Filter
Power Supply Filtering Techniques
As with any high-speed integrated circuit, power
supply filtering is very important. At a minimum,
VCCA, VCCD, and all VCCO pins should be
individually connected using a via to the power supply
plane, and separate bypass capacitors should be
used for each pin. To achieve optimal jitter
performance, each power supply pin should use
separate instances of the circuit shown in Figure 5.
Figure 5. Recommended
Power Supply Filter
Note:
For V
CCA
and V
CCD
use ferrite bead, 200mA, Murata P/N
BLM21A1025.
For V
CCO
use ferrite bead3A, 0.025
DC, Murata, P/N BLM31P005.
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| SY89538LHG | 功能描述:IC SYNTH/BUFF LVPECL/LVDS 64TQFP RoHS:是 類別:集成電路 (IC) >> 時鐘/計(jì)時 - 時鐘發(fā)生器，PLL，頻率合成器 系列:Precision Edge® 產(chǎn)品變化通告:Product Discontinuation 04/May/2011 標(biāo)準(zhǔn)包裝:96 系列:- 類型:時鐘倍頻器，零延遲緩沖器 PLL:帶旁路 輸入:LVTTL 輸出:LVTTL 電路數(shù):1 比率 - 輸入:輸出:1:8 差分 - 輸入:輸出:無/無 頻率 - 最大:133.3MHz 除法器/乘法器:是/無 電源電壓:3 V ~ 3.6 V 工作溫度:0°C ~ 70°C 安裝類型:表面貼裝 封裝/外殼:16-TSSOP（0.173"，4.40mm 寬） 供應(yīng)商設(shè)備封裝:16-TSSOP 包裝:管件 其它名稱:23S08-5HPGG |
| SY89538LHG TR | 功能描述:IC SYNTHESIZR LVPECL/LVDS 64TQFP RoHS:是 類別:集成電路 (IC) >> 時鐘/計(jì)時 - 時鐘發(fā)生器，PLL，頻率合成器 系列:Precision Edge® 產(chǎn)品變化通告:Product Discontinuation 04/May/2011 標(biāo)準(zhǔn)包裝:96 系列:- 類型:時鐘倍頻器，零延遲緩沖器 PLL:帶旁路 輸入:LVTTL 輸出:LVTTL 電路數(shù):1 比率 - 輸入:輸出:1:8 差分 - 輸入:輸出:無/無 頻率 - 最大:133.3MHz 除法器/乘法器:是/無 電源電壓:3 V ~ 3.6 V 工作溫度:0°C ~ 70°C 安裝類型:表面貼裝 封裝/外殼:16-TSSOP（0.173"，4.40mm 寬） 供應(yīng)商設(shè)備封裝:16-TSSOP 包裝:管件 其它名稱:23S08-5HPGG |
| SY89538LHGTR | 制造商:MICREL 制造商全稱:Micrel Semiconductor 功能描述:3.3V PRECISION LVPECL AND LVDS PROGRAMMABLE MULTIPLE OUTPUT BANK CLOCK SYNTHESIZER AND FANOUT BUFFER WITH ZERO DELAY |
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