參數(shù)資料
型號(hào)： SY89538L
廠商： Micrel Semiconductor,Inc.
英文描述： 3.3V PRECISION LVPECL AND LVDS PROGRAMMABLE MULTIPLE OUTPUT BANK CLOCK SYNTHESIZER AND FANOUT BUFFER WITH ZERO DELAY
中文描述： 3.3精密LVPECL和LVDS可編程多個(gè)OUTPUT銀行時(shí)鐘合成器與扇出緩沖器與零延遲
文件頁(yè)數(shù)： 21/23頁(yè)
文件大?。?/td> 628K
代理商： SY89538L
Micrel, Inc.
Output Bank and Frequency Control
There are five independently programmable output
frequency banks, four differential LVPECL output
banks and one differential LVDS output bank with
three output pairs. Each bank has frequency control
DSEL, SELx and Enx to generate different divider
ratios (see “LVPECL and LVDS Output Post-Divider
Frequency Select” Tables). It can be programmed for
pass-through, internal divided VCO clock divide-by-
/2, /8 or disable state. When disabled, the non-
inverted output goes to static LOW and the inverted
output goes to static HIGH.
Output Logic Characteristics
See “Output Termination Recommendations” for
proper termination. When LVPECL single-ended
output is desired, the unused complimentary output
should be terminated. Unused LVPECL output pairs
can be left floating. LVDS output pairs should be
terminated with 100
across the pair. In order to
minimize jitter and skew, unused LVDS output banks
and unused LVDS output pairs should be terminated
with 100
across each pair.
LVPECL Outputs:
Typical voltage swing is 800mV into 50
.
Common mode voltage is V
CCO
–1.3V.
LVDS Outputs:
Typical voltage swing is 325mV into 100
.
Common mode voltage is 1.2V.
Output Termination Recommendations
LVPECL
LVPECL has high input impedance, very low output
(open emitter) impedance, and small signal swing
which results in low EMI. LVPECL is ideal for driving
50
-and-100
-controlled impedance transmission
lines. There are several techniques for terminating the
LVPECL output: Single-ended termination, Parallel
Termination
Thevenin-Equivalent,
Y-Termination, and AC-coupled termination.
Single-Ended LVPECL Termination
Unused output pairs may be left floating. Terminating
single-ended and unused outputs will enhance the
performance. Terminate LVPECL outputs by 50
to
V
CC
–2V. The unused input terminal must be biased to
V
CC
–1.3V using a resistor network. See Figure 11h for
more details.
DC-Coupled LVPECL Parallel Termination
Terminate LVPECL by an output impedance of 50
to
V
CC
–2V. Termination resistor values are a function of
V
CC
. For a 3.3V supply, the optimal parallel
combination is 130
||82
. See Figure 12a for details.
SY89538L
October 2005
M9999-101105-B
hbwhelp@micrel.com
or (408) 955-1690
21
3-Resistor
The LVPECL output can also be terminated with three
50
resistors as shown in Figure 12b. A 0.1μF low
ESR decoupling capacitor from V
CC
to Y-Junction is
recommended in order to reduce noise in the signal.
AC-Coupled LVPECL Termination
While terminating an AC-coupled LVPECL signal, pull-
down resistor is used to create a DC current path to
GND to produce an output swing. For 3.3V supply,
100
provides the necessary pull-down. At the final
destination, proper termination to create a V
CC
–1.3V
termination bias is required 82
||130
. Please refer
to Figure 12c.
Figure 12a. LVPECL Parallel Thevenin-Equivalent
Figure 12b. LVPECL Parallel Termination
Figure 12c. LVPECL AC-Coupled Parallel
Thevenin-Equivalent
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