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參數(shù)資料
| 型號(hào)： | SY89538L |
| 廠商： | Micrel Semiconductor,Inc. |
| 英文描述： | 3.3V PRECISION LVPECL AND LVDS PROGRAMMABLE MULTIPLE OUTPUT BANK CLOCK SYNTHESIZER AND FANOUT BUFFER WITH ZERO DELAY |
| 中文描述： | 3.3精密LVPECL和LVDS可編程多個(gè)OUTPUT銀行時(shí)鐘合成器與扇出緩沖器與零延遲 |
| 文件頁數(shù)： | 10/23頁 |
| 文件大?。?/td> | 628K |
| 代理商： | SY89538L |
Micrel, Inc.
AC Electrical Characteristics
V
CCA
= V
CCD
= +3.3V ±10%; V
CCO
= +2.5V ±5% or +3.3V ±10%, R
L
(LVDS) = 100
across the output pairs, R
L
(LVPECL) = 50
into V
CCO
–2V; T
A
= –40°C to +85°C, unless otherwise stated.
Symbol
Parameter
XTAL Input Frequency Range
Reference Input Frequency Range
f
IN
Zero Delay Input Frequency Range
Phase Detector Operating
Frequency Range
SY89538L
October 2005
M9999-101105-B
hbwhelp@micrel.com
or (408) 955-1690
10
Condition
Note 7
See Table 8
See Table 9
INSEL = LOW
INSEL = HIGH
Note 8
Min
14
9.325
29.375
9.325
14
29.375
2352
Typ
Max
18
756
756
94.5
18
756
3024
75
10
Units
MHz
MHz
MHz
MHz
MHz
MHz
MHz
ps
ms
f
REF
f
OUT
f
VCO
t
SKEW
t
LOCK
Output Frequency Range
Internal VCO Frequency Range
Output-to-Output
Minimum PLL Lock Time
Loop Filter Optimized for Cycle-to-Cycle Jitter
R = 50
C1 = 0.47μF
C2 = 1000pF
1-Sigma Cycle-to-Cycle Jitter (XTAL Input)
1-Sigma Cycle-to-Cycle Jitter (RFCK Reference)
Total Jitter
Spur
15
Note 9
Note 9
Note 10
4
5
80
-35
6
14
150
ps
RMS
ps
RMS
ps
PP
dBc@
fphase
ps
RMS
kHz
t
JITTER
XTAL/RFCK Crosstalk-Induced Jitter
Note 11
See Table 10
14
≤
f
REF
≤
18
LVPECL
LVDS
See “Synchronization”
section
0.7
38.4
BW
PLL Bandwidth
11.1
t
DC
t
r,
t
f
F
OUT
Duty Cycle
Output Rise/Fall Time (20% to 80%)
Output Rise/Fall Time (20% to 80%)
43
100
80
8
50
250
150
57
400
300
%
ps
ps
t
PW_SYNC_MIN
Minimum SYNC Pulse Width
Internal
clock
cycle
Internal
clock
cycle
t
PD_SYNC
Synchronization Delay
See “Synchronization”
section
8
Notes:
7.
8.
Fundamental mode, series resonant crystal.
The output-to-output skew is defined as the worst-case difference between any outputs within a single device operating at the same voltage
and temperature.
Cycle-to-cycle jitter definition: the variation of periods between adjacent cycles, T
n
– T
n-1
where T is the time between rising edges of the
output signal.
10. Total jitter definition: with an ideal clock input of frequency <f
MAX
, no more than one output edge in 10
12
output edges will deviate by more
than the specified peak-to-peak jitter value.
11. Crosstalk is measured at the output while applying two similar differential clock frequencies that are asynchronous with respect to each
other at the inputs.
9.
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| SY89538LHG TR | 功能描述:IC SYNTHESIZR LVPECL/LVDS 64TQFP RoHS:是 類別:集成電路 (IC) >> 時(shí)鐘/計(jì)時(shí) - 時(shí)鐘發(fā)生器，PLL，頻率合成器 系列:Precision Edge® 產(chǎn)品變化通告:Product Discontinuation 04/May/2011 標(biāo)準(zhǔn)包裝:96 系列:- 類型:時(shí)鐘倍頻器，零延遲緩沖器 PLL:帶旁路 輸入:LVTTL 輸出:LVTTL 電路數(shù):1 比率 - 輸入:輸出:1:8 差分 - 輸入:輸出:無/無 頻率 - 最大:133.3MHz 除法器/乘法器:是/無 電源電壓:3 V ~ 3.6 V 工作溫度:0°C ~ 70°C 安裝類型:表面貼裝 封裝/外殼:16-TSSOP（0.173"，4.40mm 寬） 供應(yīng)商設(shè)備封裝:16-TSSOP 包裝:管件 其它名稱:23S08-5HPGG |
| SY89538LHGTR | 制造商:MICREL 制造商全稱:Micrel Semiconductor 功能描述:3.3V PRECISION LVPECL AND LVDS PROGRAMMABLE MULTIPLE OUTPUT BANK CLOCK SYNTHESIZER AND FANOUT BUFFER WITH ZERO DELAY |
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