參數(shù)資料
型號： SY89538L
廠商： Micrel Semiconductor,Inc.
英文描述： 3.3V PRECISION LVPECL AND LVDS PROGRAMMABLE MULTIPLE OUTPUT BANK CLOCK SYNTHESIZER AND FANOUT BUFFER WITH ZERO DELAY
中文描述： 3.3精密LVPECL和LVDS可編程多個OUTPUT銀行時鐘合成器與扇出緩沖器與零延遲
文件頁數(shù)： 19/23頁
文件大?。?/td> 628K
代理商： SY89538L
Micrel, Inc.
SY89538L
October 2005
M9999-101105-B
hbwhelp@micrel.com
or (408) 955-1690
19
Figure 6 shows the open and closed loop gain of the
SY89538L. The closed loop-gain plot shows that the
SY89538L when configured with the recommended
loop filter values has essentially no jitter peaking near
the -3dB point. In addition, the open loop curve shows
the frequency at which unity gain occurs for a typical
case of the SY89538L with V
CC
= 3.3V at T
A
= 25°C.
At unity gain, Figure 7 can be used to determine the
phase margin or stability of the SY89538L.
Figure 6. Open and Closed Loop Gain
at V
CC
= 3.3V, T
A
= 25°C
Figure 7. Phase Margin Plot
at V
CC
= 3.3V, T
A
= 25°C
Figure 8 illustrates the VCO frequency versus the loop
filter control voltage at 3.3V, T
A
= 25°C. The normal
loop filter control voltage is -300mV to +300mV.
Figure 9 illustrates the VCO gain curve at V
CC
= 3.3V,
T
A
= 25°C. With this set of information, determining
the loop stability with other sets of loop filter
configurations is possible.
Figure 8. Loop Filter Control Voltage vs.
Frequency at 3.3V, T
A
= 25°C
Figure 9. Frequency vs.
Loop Filter Control Voltage at 3.3V, T
A
= 25°C
Input Interface
RFCK and FBIN are designed to accept any
differential or single-ended input signal 300mV above
V
CC
or 300mV below GND. RFCK and FBIN should
not be left floating. Tie either the true or complement
input to GND, but not both. A logic zero is achieved by
connecting the complement input to GND with the true
input floating. For TTL input, tie a 2.5k
resistor
between the complement input and GND. LVDS, CML
and HSTL differential signals may be connected
directly to the reference inputs.
Figure 10. Simplified Input Structure
d
P
Frequency (Hz)
Frequency (Hz)
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