![](http://datasheet.mmic.net.cn/370000/STDL80_datasheet_16733660/STDL80_8.png)
STDL80
viii
SEC ASIC
Decoders
DC4...............................................................................................................................................3-291
DC4I..............................................................................................................................................3-293
DC8I..............................................................................................................................................3-295
Adders
FA/FAD2........................................................................................................................................3-300
HA/HAD2.......................................................................................................................................3-303
Multiplexers
MX2/MX2D3..................................................................................................................................3-306
MX2X4 ..........................................................................................................................................3-308
YMX2/YMX2D2.............................................................................................................................3-311
MX2I/MX2ID2................................................................................................................................3-313
MX2IA/MX2ID2A...........................................................................................................................3-315
MX2IX4 .........................................................................................................................................3-317
MX3I/MX3ID2................................................................................................................................3-320
MX4/MX4D2..................................................................................................................................3-322
YMX4/YMX4D2.............................................................................................................................3-325
MX5/MX5D2..................................................................................................................................3-328
MX8/MX8D2..................................................................................................................................3-331
YMX8/YMX8D2.............................................................................................................................3-334
4
Input/Output Cells
Overview .......................................................................................................................................4-1
Summary Tables ...........................................................................................................................4-2
Input Buffers
PvIC/PvICD/PvICU........................................................................................................................4-7
PvIS/PvISD/PvISU ........................................................................................................................4-10
Output Buffers
PvOByz .........................................................................................................................................4-14
PvODyz.........................................................................................................................................4-19
PvOTyz..........................................................................................................................................4-26
Bi-Directional Buffers
PvBaDyz/PvBaUDyz.....................................................................................................................4-37
PvBaTyz/PvBaDTyz/PvBaUTyz.....................................................................................................4-37
Input Clock Drivers
PSCKDCy/PSCKDCDy/PSCKDCUy.............................................................................................4-39
PSCKDSy/PSCKDSDy/PSCKDSUy .............................................................................................4-46