
INTRODUCTION TO STDL80
PRODUCT FAMILY
SEC ASIC
1-3
STDL80
< Input/Output Cells >
There are about 400 different I/O buffers. Each I/O cell
is implemented solely on the basic I/O cell architecture
which forms the periphery of the masterslice.
A test logic is provided to enable the efficient
parametric (threshold voltage) testing on input buffers
including CMOS and TTL level converters, Schmitt
trigger input buffers, clock drivers and oscillator
buffers. Pull-up and pull-down resistors are optional
features.
Three basic types of output buffers (non-inverting, tri-
state and open drain) are available in a range of
driving capabilities from 1mA to 24mA. The slew rate
control is provided for each buffer type (except 1mA
and 2mA buffers) to reduce output power/ground bus
noise and signal ringing, especially in simultaneous
switching outputs.
Bi-directional buffers are combinations of input buffers
and output buffers (tri-state or open drain) in a single
unit. The bi-directional output drive capability of 5V
tolerant I/O is in the range of 1mA to 6mA. The I/O
structure has been fully characterized for ESD
protection and latch-up resistance.
For user’s convenience, STDL80 library provides with
three options of pull-down and pull-up resistances
respectively. They are 50K
,
100K
, and 200K
(The default value is 100K
).
I/O Cell Drive Options
To provide designers with the greater flexibility, each I/
O buffer can be selected among various current levels
(e.g., 1mA, 2mA, ..., 24mA). The choice of current-
level for I/O buffers affects their propagation delay and
current noise.
The slew rate control helps decrease the system noise
and output signal overshoot/undershoot caused by the
switching of output buffers. The output edge rate can
be slowed down by selecting the high slew rate control
cells. STDL80 provides three different sets of output
slew rate controls. Only one I/O slot is required for any
slew rate control options.
5V Tolerant I/O Buffers
STDL80 library is a process which has the most
optimum performance in 3.3V. In this process,
voltages more than 3.6V are not allowed at the gate
oxide because of a reliability problem. And a special
circuit is adopted in order to make pin voltage tolerable
up to 5.25V and to offer TTL interface driving up to
6mA. Obviously, this circuit is constructed not to
permit more than 3.6 voltages at the gate oxide. The
external circuit diagram is as follows.
The maximum external tolerance voltage of this buffer
is 5.5V. And the leakage current of tri-state input pin
and output pin is less than 10nA in 0 ~ 5V and less
than 70
μ
A in 5.5V. When the output is tri-state and the
output pin voltage is 5V, 5V of bulk bias voltage is
required to prevent current from flowing through a
chip, however, almost no current flows. If the bulk bias
is 3.3V, it operates as a 3.3V normal buffer.
PCI Buffers
In addition to input, output, bi-directional, slew rate
controlled and Schmitt trigger I/O buffers, SEC ASIC
now offers PCI (Peripheral Component Interconnect) I/
O buffers. PCI is expected to be better suited to the
more complex and feature-rich design than the
existing local bus standards. 5V tolerant and 3.3V PCI
buffers are included in this library.
Core 3.3V I/O bias 5.0V 3.3V
5.0V
Output voltage
3.3V
Open drain output
5V tolerant input
Tri-state output
Bi-directional I/O
0.5
μ
m 3.3V process
Normal 5V process