INTRODUCTION TO STDL80
POWER DISSIPATION
SEC ASIC
1-7
STDL80
POWER DISSIPATION
Estimation of Power Dissipation in CMOS
Circuit
CMOS circuits have been traditionally considered to
consume low power since they draw very small
amount of current in a steady state. However, the
recent revolution in a CMOS technology that allows
very high gate density has changed the way the power
dissipation should be understood. The power
dissipation in a CMOS circuit is affected by various
factors such as the number of gates, a switching
frequency, the loading on the output of a gate, and so
on.
Power dissipation is important when designers decide
the amount of necessary power supply current for the
device to operate in safety. Propagation delays and a
reliability of the device also depend on the power
dissipation which determines the temperature at which
the die operates. To obtain a high speed and a
reliability, designers must estimate the power
dissipation of the device accurately and determine the
appropriate environments including packages and
system cooling methods.
This section describes the concept of two types of
power dissipation (static and dynamic) in a CMOS
circuit, the method of calculating them in the SEC
STDL80 library, and finally their relationship with a
temperature.
Static (DC) Power Dissipation
There are two types of static or DC current
contributing to the total static power dissipation in
CMOS circuits.
One is the leakage current of the gates resulted by a
reverse bias between a well and a substrate region.
There is no DC current path from power to ground in a
CMOS because one of the transistor pair is always off,
therefore, no static current except the leakage current
flows through the internal gates of the device. The
amount of this leakage current is, however, in the
range of tens of nano amperes, which is negligible.
The other is DC current that flows through the input
and output buffers when the circuit is interfaced with
other devices, especially TTL. The current of pull-up/
pull-down transistor included in the input buffers is
about 50
μ
A typically, which is also negligible.
Therefore, only DC current that the output buffers
source or sink has to be counted to estimate the total
static power dissipation.
DC power dissipation of TTL output and bi-directional
buffers is determined by the following formula:
P
DC_TTL_ OUTPUT
=
∑
(V
OL
x I
OL
x t
L
) +
∑
((V
DD
– V
OH
) x I
OH
x t
H
)
,where
t
H
= T
HIGH
/ T,
t
L
+ t
H
= 1.
Dynamic (AC) Power Dissipation
When a CMOS gate changes its state, it draws
switching current as a result of charging or discharging
of a node capacitance, C
L
. The energy associated with
the switching current for a node capacitance, C
L
, is
1 / 2 x (C
L
x V
DD2
)
,where V
DD
is a power supply voltage.
The switching occurs twice per cycle for periodic
signals: once for charging a capacitance and once for
discharging it. Hence, the dynamic power dissipation
due to the switching current is the energy divided by
the clock period and multiplied by the factor of two, or
C
L
x V
DD
x V
DD
/ T
,where T is a clock period.
As shown above, it is quite straight forward to calculate
the dynamic power dissipation for a single gate. The
dynamic power dissipation for an entire chip is,
however, much more complicated to estimate since it
depends on the degree of switching activity of the
circuit. SEC has found that the degree of switching
activity is 20% on the average and recommends to use
this number to estimate the total dynamic power
dissipation.