STDL80
iv
SEC ASIC
Table of Contents
1
Introduction to STDL80
Library Description........................................................................................................................1-1
Features........................................................................................................................................1-1
CAE Support.................................................................................................................................1-2
Product Family ..............................................................................................................................1-2
Internal Macrocells ...............................................................................................................1-2
Macrofunctions .....................................................................................................................1-2
Megafunctions ......................................................................................................................1-2
Memory Compilers ...............................................................................................................1-2
Datapath Compilers..............................................................................................................1-2
Input/Output Cells.................................................................................................................1-3
V
DD
/V
SS
Rules and Guidelines .....................................................................................................1-6
Power Dissipation..........................................................................................................................1-7
Propagation Delays.......................................................................................................................1-9
Delay Model ..................................................................................................................................1-12
Maximum Fanouts.........................................................................................................................1-14
Product Line-Up ............................................................................................................................1-20
Packages.......................................................................................................................................1-20
Dedicated Corner V
DD
/V
SS
Pads..................................................................................................1-21
Testability Design Methodology.....................................................................................................1-21
External Design Interface Considerations.....................................................................................1-22
Crystal Oscillator Considerations..................................................................................................1-28
2
Electrical Characteristics
DC Electrical Characteristics.........................................................................................................2-1
Input Buffer DC Curves.................................................................................................................2-3
Output Drive Capabilities...............................................................................................................2-5
3
Internal Macrocells
Overview .......................................................................................................................................3-1
Summary Tables ...........................................................................................................................3-2
Logic Cells
AD2/AD2D2...................................................................................................................................3-11
AD3/AD3D3...................................................................................................................................3-12