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Samsung ASIC
ix
STDL130
Contents
LD3_LP/LD3D2_LP.......................................................................................................................3-325
LD4_LP/LD4D2_LP.......................................................................................................................3-328
LD5_LP/LD5D2_LP.......................................................................................................................3-331
LD5Q_LP/LD5QD2_LP.................................................................................................................3-333
LD6_LP/LD6D2_LP.......................................................................................................................3-335
LD6Q_LP/LD6QD2_LP.................................................................................................................3-338
Bus Holder
BUSHOLDER_LP..........................................................................................................................3-340
Input Clock Driver
CK2_LP/CK4_LP/CK6_LP/CK8_LP..............................................................................................3-341
Adders
FA_LP/FAD2_LP ...........................................................................................................................3-344
HA_LP/HAD2_LP..........................................................................................................................3-346
Multiplexers
MX2_LP/MX2D2_LP/MX2D4_LP..................................................................................................3-349
MX2I_LP/MX2ID2_LP/MX2ID4_LP...............................................................................................3-352
MX2IA_LP/MX2ID2A_LP/MX2ID4A_LP........................................................................................3-354
MX4_LP/MX4D2_LP/MX4D4_LP..................................................................................................3-357
MX8_LP/MX8D2_LP/MX8D4_LP..................................................................................................3-361
Integrated Clock-Gating Cells
CGLP_LP/CGLPD2_LP/CGLPD4_LP...........................................................................................3-370
4
Input/Output Cell
Overview .......................................................................................................................................4-1
Summary Tables ...........................................................................................................................4-2
Input Buffers
PvIC_LP/PvICD_LP/PvICU_LP.....................................................................................................4-11
PvIS_LP/PvISD_LP/PvISU_LP.....................................................................................................4-18
Output Buffers
PvOByz_LP...................................................................................................................................4-26
PvODyz_LP...................................................................................................................................4-42
PvOTyz_LP....................................................................................................................................4-64
Bi-Directional Buffers
PvBaDyz_LP/PvBaUDyz_LP ........................................................................................................4-102
PvBaTyz_LP/PvBaDTyz_LP/PvBaUTyz_LP..................................................................................4-102
Input Clock Drivers