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1.9 Power Dissipation
Introduction
STDL130
1-32
Samsung ASIC
1.9
Power
Dissipation
1.9.1 ESTIMATION OF POWER DISSIPATION IN CMOS CIRCUIT
A primary advantage of CMOS circuits is low power consumption since they draw
a very small amount of current under steady state, DC conditions. However, as
circuit densities and clock rates increase, the power dissipation in CMOS circuits
becomes substantial. Power dissipation in CMOS circuits is affected by various
factors such as the number of gates, the switching frequency, and gate output
loading.
Circuit operating temperature is an important factor in determining circuit speed
and reliability. Circuit power dissipation is a major factor in determining circuit
operating temperature. Designers must estimate the power dissipation of a circuit
accurately and choose the appropriate package and system operating conditions
for the circuit to insure the best performance and reliability.
The following sections describe the components of power dissipation in a CMOS
circuit (static and dynamic), and the method of calculating them for the Samsung
STDL130 library elements.
1.9.2 STATIC (DC) POWER DISSIPATION
Two types of static or DC current contribute to the total static power dissipation in
CMOS circuits - leakage current and input/output current.
Leakage current results from a reverse bias between the well and the substrate
region of the CMOS circuit. Since there is no DC current path from power to
ground through a CMOS logic gate in steady state, no static current except
leakage current flows through the internal circuitry of a CMOS device. The
amount of this leakage current is normally on the order of tens of nano amperes
and is negligible.
Input/output current flows through I/O buffers when the circuit is interfaced with
other devices, especially TTL. The current of pull-up/pull-down transistor in the
input buffers is typically on the order of tens of micro amperes (33
μ
A at 3.3V,
25
μ
A at 2.5V, and 18
μ
A at 1.8V), which is also negligible. Therefore, only the DC
currentthat theoutput buffers sourceor sinkneeds to becounted toestimate total
static power dissipation. The DC power dissipation of output and bi-directional
buffers is determined by the following formula:
n
∑
where,
n = Number of output and bidirectional buffers
T = Total operation time in output mode
t
H
= The sum of logic high state time
t
L
= The sum of logic low state time
t
L
+ t
H
= T (assuming that output and bi-directional buffers are not tri-state)
S
out
is the output mode ratio of bi-directional buffers (typically 0.5)
P
DC_OUTPUT
[mW]
V
OL k
( )
I
OL k
( )
t
L k
( )
×
×
(
)
k
1
=
V
DD
V
OH k
( )
–
(
)
I
OH k
( )
t
H k
( )
×
×
(
)
k
1
=
n
∑
+
T
=
P
DC_BI
[mW]
V
OL k
( )
I
OL k
( )
t
L k
( )
×
×
(
)
k
1
=
n
∑
V
DD
V
OH k
( )
–
(
)
I
OH k
( )
t
H k
( )
×
×
(
)
k
1
=
n
∑
+
S
out
T
×
=