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1.11 Crystal Oscillator Consideration
Introduction
STDL130
1-44
Samsung ASIC
1.11.2.3 Oscillation Frequency
The oscillation frequency is mainly determined by the crystal. The on-chip
oscillator has little effect on the frequency.
The influence of the on-chip oscillator on frequency results from its input and
output (pin-to-ground) capacitances which parallel C1 and C2, and the PADA-to-
PADY (pin-to-pin) capacitance which parallels the crystal. The input and pin-to-
pin capacitances are about 7pF each.
1.11.2.4 C1 and C2 Selection
Optimal values for C1 and C2 depend on whether a quartz crystal or ceramic
resonator is being used, and on application-specific requirements for start-up
time and frequency tolerance.
Start-up time is sometimes more critical in microcontroller systems than
frequency stability because of various reset and initialization requirements.
Accuracy of the oscillator frequency is less commonly critical, as when the
oscillator is being used as a time base. As a general rule, fast start-up and stable
frequency tend to pull the oscillator design in opposite directions.
Considerations of both start-up time and frequency stability over temperature
suggest that C1 and C2 should be about equal and at least 15pF (but they don’t
have to be either).
Increasing the value of these capacitors above 40pF or 50pF improves frequency
stability, but also increases the start-up time. If the capacitors are too large
(several hundred pF), the oscillator won’t start up at all.
1.11.2.5 Rf and Rx Selection
A large Rf (1M ohm) holds the on-chip oscillator (a CMOS inverter) in it linear
region allowing it to oscillate. The inverter has a fairly low output resistance which
de-stabilizes the oscillator circuit. Rx of several K-ohms is added to the feedback
network, as shown in Figure 1-15, to stabilize the oscillator circuit.
At higher oscillator frequencies, a 20pF or 30pF capacitor is sometimes used in
place of Rx to compensate for internal propagation delay.
1.11.3 PCB CONSIDERATIONS
Noise glitches arising at PADA or PADY pins at the wrong time can cause a
miscount in the internal clock-generating circuitry. These kinds of glitches can be
produced through capacitive coupling between the oscillator components and
PCB traces carrying digital signals with fast rise and fall times.
For this reason, the oscillator components should be mounted close to the chip
and have short, direct traces to the PADA, PADY, and VSS pins. If possible, use
dedicated V
SS
and V
DD
pins for the on-chip oscillator.
In addition, surrounding oscillator components with “quiet” traces (V
DD
and V
SS
)
will alleviate capacitive coupling to signals having fast edges. To minimize
inductive coupling, the PCB layout should minimize lead, wire, and trace lengths
for oscillator components.