
Samsung ASIC
3-55
STDL130
NR4
_
LP/NR4D2
_
LP/NR4D4
_
LP
4-Input NOR with 1X/2X/4X Drive
Logic Symbol
Cell Data
Switching Characteristics
NR4_LP
(Typical process, 25
°
C, 1.8V, t
R
/t
F
= 0.20ns, SL: Standard Load)
Input Load (SL)
NR4D2_LP
B
0.7
Gate Count
NR4D2_LP
4.00
NR4_LP
B
0.7
NR4D4_LP
B
0.7
A
C
0.8
D
0.7
A
C
0.8
D
0.8
A
C
0.8
D
0.8
0.8
0.8
0.8
NR4_LP
3.67
NR4D4_LP
5.00
Y
A
B
C
D
Path
Parameter
Delay [ns]
SL = 2
0.100
0.085
0.266
0.226
0.101
0.084
0.286
0.240
0.100
0.088
0.267
0.244
0.099
0.088
0.289
0.259
<
Delay Equations [ns]
Group1*
0.048 + 0.026*SL
0.049 + 0.018*SL
0.237 + 0.014*SL
0.199 + 0.014*SL
0.049 + 0.026*SL
0.046 + 0.019*SL
0.258 + 0.014*SL
0.213 + 0.013*SL
0.047 + 0.027*SL
0.051 + 0.018*SL
0.239 + 0.014*SL
0.216 + 0.014*SL
0.047 + 0.026*SL
0.052 + 0.018*SL
0.260 + 0.014*SL
0.232 + 0.014*SL
Group2*
0.043 + 0.027*SL
0.049 + 0.018*SL
0.241 + 0.013*SL
0.207 + 0.011*SL
0.044 + 0.027*SL
0.050 + 0.018*SL
0.261 + 0.013*SL
0.221 + 0.011*SL
0.046 + 0.027*SL
0.052 + 0.018*SL
0.243 + 0.013*SL
0.225 + 0.012*SL
0.043 + 0.027*SL
0.048 + 0.019*SL
0.264 + 0.013*SL
0.240 + 0.012*SL
Group3*
0.040 + 0.028*SL
0.044 + 0.019*SL
0.242 + 0.013*SL
0.212 + 0.011*SL
0.041 + 0.028*SL
0.044 + 0.019*SL
0.263 + 0.013*SL
0.226 + 0.011*SL
0.040 + 0.028*SL
0.046 + 0.019*SL
0.244 + 0.013*SL
0.231 + 0.011*SL
0.040 + 0.028*SL
0.047 + 0.019*SL
0.266 + 0.013*SL
0.246 + 0.011*SL
A to Y
tR
tF
tPLH
tPHL
tR
tF
tPLH
tPHL
tR
tF
tPLH
tPHL
tR
tF
tPLH
tPHL
B to Y
C to Y
D to Y
*Group1 : SL < 4, *Group2 : =
Truth Table
A
0
B
0
Other States
C
0
D
0
Y
1
0