參數資料
型號： ST623X-KIT
英文描述： 8 MBIT (X8, BLOCK ERASE) FLASH MEMORY
中文描述： 入門套件小冊子的ST6230
文件頁數： 5/86頁
文件大?。?/td> 531K
代理商： ST623X-KIT
5/86
ST62T30B ST62E30B
1 GENERAL DESCRIPTION
1.1 INTRODUCTION
The ST62T30B and ST62E30B devices are low
cost members of the ST62xx 8-bit HCMOS family
of microcontrollers, which is targetedat low to me-
dium complexity applications. All ST62xx devices
are based on a building block approach: a com-
mon core is surrounded by a number of on-chip
peripherals.
The ST62E30B is the erasable EPROMversion of
the ST62T30B device, which may be used to em-
ulate the ST62T30B device, as well as the respec-
tive ST6230B ROM devices.
Figure 1. Block Diagram
TEST
NMI
INTERRUPT
PROGRAM
Memory
PC
STACK LEVEL 1
STACK LEVEL 2
STACK LEVEL 3
STACK LEVEL 4
STACK LEVEL 5
STACK LEVEL 6
POWER
SUPPLY
OSCILLATOR
RESET
DATA ROM
USER
SELECTABLE
DATA RAM
192 Bytes
PORT A
PORT B
TIMER
DIGITAL
WATCHDOG
8 BIT CORE
TEST/V
PP
8-BIT
A/D CONVERTER
PA0..PA1 / 20 mA Sink
PA2/OVF/ 20 mA Sink
PA3/PWM/20 mA Sink
PA4/Ain/CP1
PA5/Ain/CP2
V
DD
V
SS
OSCin OSCout
RESET
PORT C
SPI (SERIAL
PERIPHERAL
INTERFACE)
AUTORELOAD
TIMER
7948
bytes
DATA EEPROM
128 Bytes
PB4..PB6/Ain
PC4..PC7/Ain
PORT D
PD6,PD7/Ain
PD1/Ain/Scl
PD2/Ain/Sin
PD3/Ain/Sout
PD4/Ain/RXD1
PD5/Ain/TXD1
(V
PP
on EPROM/OTP versions only)
TIMER
VR01823F
UART
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