參數(shù)資料
型號(hào): ST623X-KIT
英文描述: 8 MBIT (X8, BLOCK ERASE) FLASH MEMORY
中文描述: 入門套件小冊(cè)子的ST6230
文件頁數(shù): 41/86頁
文件大?。?/td> 531K
代理商: ST623X-KIT
41/86
ST62T30B ST62E30B
PA4/CP1 or PA5/CP2 pins must be configured as
input through DDR register to allow CP1 or CP2
triggered input capture of theARTimer16. All input
modes are available and I/O’s can be read inde-
pendently of the ARTimer at any time. As long as
RLDSEL2, RLDSEL1 bits do not enable CP1 or
CP2 triggeredcapture, PA4/CP1and PA5/CP2 are
standard I/O’s configurable through DDR and OR
registers.
5.0.2 SPI alternate functions
PD2/Sin and PD1/Scl pins must be configured as
input through the DDR and OR registers to be
used as data in and data clock (Slave mode) for
the SPI. All input modes are available and I/O’s
can be read independently of the SPI at any time.
PD3/Sout must be configured in open drainoutput
mode to be used as data out for the SPI. In output
mode, thevalue present on the pin is the port data
register content only if PD3 is defined as push pull
output, while serial transmission is possible only in
open drain mode.
5.0.3 UART alternate functions
PD4/RXD1 pin must be configured as input
through the DDR and OR registers to be used as
reception line for the UART. All input modes are
available and PD4 can be read independently of
the UART at any time.
PD5/TXD1 pin must be configured as output
through the DDR and OR registers to be used as
transmission line for the UART. Value present on
the pin in output mode is the Data register content
as long as no transmission is active.
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