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參數(shù)資料
| 型號： | ST623X-KIT |
| 英文描述： | 8 MBIT (X8, BLOCK ERASE) FLASH MEMORY |
| 中文描述： | 入門套件小冊子的ST6230 |
| 文件頁數(shù)： | 37/86頁 |
| 文件大?。?/td> | 531K |
| 代理商： | ST623X-KIT |
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ST62T30B ST62E30B
4 ON-CHIP PERIPHERALS
4.1 I/O PORTS
The MCU features Input/Output lines which may
be individuallyprogrammedas any of thefollowing
input or output configurations:
– Input without pull-up or interrupt
– Input with pull-up and interrupt
– Input with pull-up, but without interrupt
– Analog input
– Push-pull output
– Open drain output
The lines are organised as bytewise Ports.
Each port is associated with 3 registers in Data
space. Each bit of these registers is associated
with a particular line (for instance, bits 0 of Port A
Data, Direction and Option registers are associat-
ed with the PA0 line of Port A).
The DATA registers (DRx), are used to read the
voltage level values of the lines which have been
configured as inputs, or to write the logic value of
the signal to be output on the lines configured as
outputs. The port data registers can be readto get
the effective logic levels of the pins, but they can
be also written by user software, in conjunction
with the related option registers, to select the dif-
ferent input mode options.
Single-bit operations on I/O registers are possible
but care is necessary because reading in input
mode is done from I/O pins while writing will direct-
ly affect the Port data register causing an unde-
sired change of the input configuration.
The Data Direction registers (DDRx) allow the
data direction (input or output) of each pin to be
set.
The Option registers (ORx) are used to select the
different port options available both in input and in
output mode.
All I/O registers can be read or written to just as
any other RAM location in Data space, so no extra
RAM cells are needed for port data storage and
manipulation. During MCU initialization, all I/Oreg-
isters are cleared andthe input mode with pull-ups
and no interrupt generation is selected for all the
pins, thus avoiding pin conflicts.
Figure 21. I/O Port Block Diagram
V
DD
RESET
S
IN
CONTROLS
S
OUT
SHIFT
REGISTER
DATA
REGISTER
DATA
DIRECTION
REGISTER
OPTION
REGISTER
INPUT/OUTPUT
TO INTERRUPT
V
DD
TO ADC
VA00413
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