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參數(shù)資料
| 型號： | ST623X-KIT |
| 英文描述： | 8 MBIT (X8, BLOCK ERASE) FLASH MEMORY |
| 中文描述： | 入門套件小冊子的ST6230 |
| 文件頁數(shù)： | 48/86頁 |
| 文件大?。?/td> | 531K |
| 代理商： | ST623X-KIT |
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48/86
ST62T30B ST62E30B
The maximum time for downcounting is therefore
2
16
x Psc x Tclk where Psc is the prescaler ratio,
and Tclk the period of the main oscillator.
This down counter is stopped and its content kept
cleared as long as RUNRES bit is cleared.
5.2.1.1 Reload functions
The 16-bit down counter can be reloaded 3 differ-
ent ways:
At a zerooverflow occurrence with the bitRELOAD
cleared: The counter is reloaded to FFFFh.
At a zero overflow occurrence with the bit
RELOAD set: The counter is reloaded with the val-
ue programmed in the RLCP register. For each
overflow, the transitionbetween 0000h and the re-
load value(RLCP orFFFFh) is flagged through the
OVFFLG bit.
At an external event on pin CP1 or CP2 with the bit
RELOAD set: The counter is reloaded with the val-
ue programmed in the RLCP register.
As a consequence, the time between a timer re-
load and a zero overflow occurrence depends on
the value in RLCP when RELOAD bit is set. This
time is equal to (RLCP+1) x Psc x Tclk when
RELOAD bit is set, while it is 2
16
xPsc xTclk when
RELOAD bit is cleared.
5.2.1.2 Compare functions
The value in the counter CT is continuously com-
pared to 0000h and to the value programmed into
the Compare Register CMP. The comparison
range to 0000h and CMP is defined by using the
MASK registerto select which bits are used, there-
fore the comparisons performed are:
– MASK&CT =
MASK&CMP.
– MASK&CT =0000h.
When a
matched comparison
MASK&CMP occurs, the flags ZEROFLG and
COMPFLG are respectively set.
By using MASK values reported in Table 17, the
MASK register works as counter frequency multi-
plier for the compare functions. In that case posi-
tive masked comparison occur with a period of
2
(n+1)
x Psc x Tclk where n is the position of the
most significant bit of MASK value.
Table 17. Recommended Mask Values
to 0000h or
Note
: Writing 0000h inMASK gives a period equal
to two times the prescaled period Psc x Tclk.
Figure 27. Flags Setting in Compare and Reload Functions
Hexadecimal
Binary
MSbit at 1
position,n
15
14
13
12
11
FFFFh
7FFFh
3FFFh
1FFFh
0FFFh
...
0007h
0003h
0001h
1111 1111 1111 1111
0111 1111 1111 1111
0011 1111 1111 1111
0001 1111 1111 1111
0000 1111 1111 1111
...
0000 0000 0000 0111
0000 0000 0000 0011
0000 0000 0000 0001
2
1
0
CMP
Counter
Value CT
ZEROFLG
0
FFFFh
or
RLCP
Software Reset
Software Reset
Software Reset
OVFFLG
COMPFLG
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