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| 型號： | ST52513K2 |
| 英文描述： | MAX 3000A CPLD 32 MC 44-PLCC |
| 中文描述： | 8位重癥監(jiān)護(hù)病房，10位ADC。兩個(gè)定時(shí)器/脈寬調(diào)制。 I2C總線。的SPI。脊髓損傷。提供了8K閃存 |
| 文件頁數(shù)： | 98/106頁 |
| 文件大?。?/td> | 1355K |
| 代理商： | ST52513K2 |
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13.5 Register Description
In the following sections describe the registers
used by the I2C Interface are described.
13.5.1 I2C Interface Configuration Registers.
I2C Control Register (I2C_CR)
Configuration Register 16 (010h) Read/Write
Reset Value: 0000 0000 (00h)
Bit 7-6: Not Used.They must be held to 0.
Bit 5: PE Peripheral Enable.
This bit is set and cleared by software
0: peripheral disabled
1: peripheral enabled
Notes:
– When PE=0, all the bits of the I2C_CR register
and the SR register except the Stop bit are reset.
All outputs are released while PE=0
– When PE=1, the corresponding I/O pins are se-
lected by hardware as alternate functions.
– To enable the I2C interface, write the I2C_CR
register TWICE with PE=1 as the first write only
activates the interface (only PE is set).
Bit 4: ENGC Enable General Call
This bit is set and cleared by software. It is
also cleared by hardware when the interface
is disabled (PE=0).
0: General Call disabled
1: General Call enabled
Note:
The
00h
General
Call
address
is
acknowledged (01h ignored).
Bit 3: START Generation of a Start Condition
This bit is set and cleared by software. It is
also cleared by hardware when the interface
is disabled (PE=0) or when the Start
condition is sent (with interrupt generation if
ITE=1).
– In Master Mode
0: No Start generation
1: Repeated Start generation
– In Slave Mode
0: No Start generation
1: Start generation when the bus is free
Bit 2: ACK Acknowledge enable
This bit is set and cleared by software. It is
also cleared by hardware when the interface
is disabled (PE=0).
0: No acknowledge returned
1: Acknowledge returned after an address
byte or a data byte is received
Bit 1: STOP Reset signal mode
This bit is set and cleared by software. It is
also cleared by hardware in master mode.
Note: This bit is not cleared when the
interface is disabled (PE=0).
– In Master Mode
0: No Stop generation
1: Stop generation after the current byte
transfer or after the current Start condition
is sent. The STOP bit is cleared by
hardware when the Stop condition is sent.
– In Slave Mode
0: No actions performed
1: Release the SCL and SDA lines after the
last
byte
transfer
(BTF=1)
in
slave
transmitter mode. In this mode the STOP
bit has to be cleared by software.
Bit 0: ITE Interrupt Enable
0: Interrupt disabled
1: Interrupt enabled
I2C Clock Control Register (I2C_CCR)
Configuration Register 17 (011h) Read/Write
Reset Value: 0000 0000 (00h)
Bit 7: FM/SM Fast/Standard I2C Mode.
This bit is set and cleared by software. It is
not cleared when the interface is disabled
(PE=0).
70
-
PE
ENGC
START
ACK
STOP
ITE
70
FM/SM
CC6
CC5
CC4
CC3
CC2
CC1
CC0
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相關(guān)代理商/技術(shù)參數(shù) |
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| ST52513K3 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:8-BIT ICU WITH 10-BIT ADC. TWO TIMERS/PWM. I2C. SPI. SCI. UP TO 8K FLASH |
| ST52513Y2 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:8-BIT ICU WITH 10-BIT ADC. TWO TIMERS/PWM. I2C. SPI. SCI. UP TO 8K FLASH |
| ST52513Y3 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:8-BIT ICU WITH 10-BIT ADC. TWO TIMERS/PWM. I2C. SPI. SCI. UP TO 8K FLASH |
| ST52514F1 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:8-BIT ICU WITH 10-BIT ADC. TWO TIMERS/PWM. I2C. SPI. SCI. UP TO 8K FLASH |
| ST52514F3 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:8-BIT ICU WITH 10-BIT ADC. TWO TIMERS/PWM. I2C. SPI. SCI. UP TO 8K FLASH |
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