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參數(shù)資料
| 型號： | ST52513K2 |
| 英文描述： | MAX 3000A CPLD 32 MC 44-PLCC |
| 中文描述： | 8位重癥監(jiān)護病房，10位ADC。兩個定時器/脈寬調(diào)制。 I2C總線。的SPI。脊髓損傷。提供了8K閃存 |
| 文件頁數(shù)： | 15/106頁 |
| 文件大?。?/td> | 1355K |
| 代理商： | ST52513K2 |
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2 ADDRESSING SPACES
ST52F501L/F502L has six separate addressing
spaces:
s
Register File
s
Program/Data Memory
s
Stacks
s
Input Registers
s
Output Registers
s
Configuration Registers
Each space is addressed by a load type instruction
that indicates the source and the destination space
in the mnemonic code (see Figure 2.1).
2.1 Memory Interface
The read/write operation in the space addresses
are managed by the Memory Interface, which can
recognize the type of memory addressed and set
the appropriate access time and mode.
In addition, the Memory Interface manages the In
Application Programming (IAP) functions in Flash
devices like writing cycle and memory write
protection.
Figure 2.1 Addressing Spaces
2.2 Register File
The Register File consists of 256 general purpose
8-bit RAM locations called “registers” in order to
recall the functionality.
The Register File exchanges data with all the other
addressing spaces and is used by the ALU to
perform all the arithmetic and logic instructions.
These instructions have any Register File address
as operands.
Data can be moved from one location to another by
using the LDRR instruction; see further ahead for
information on the instruction used to move data
between
the
Register
File
and
the
other
addressing spaces.
2.3 Program/Data Memory
The Program/Data Memory consists of both non-
volatile memory (Flash, EEPROM) and RAM
memory benches.
Non-volatile memory (NVM) is mainly used to store
the user program and can also be used to store
permanent data (constant, look-up tables).
Each RAM bench consists of 256 locations used to
store run-time user data. At least one bench is
present in the devices. RAM benches are also
used to implement both System and User Stacks.
CU
DPU
ALU
PERIPHERAL
BLOCK
REGISTER FILE
INPUT REGISTERS
NON VOLATILE MEMORY
RAM BANKS
AND STACKS
PROGRAM/DATA MEMORY
STFive CORE
ON CHIP PERIPHERALS
OUTPUT
REGISTERS
CONFIGURATION
REGISTERS
PERIPHERAL
BLOCK
PERIPHERAL
BLOCK
LDER
LDRE
LDRI
LDCE
LDCR
DECISION
PROCESSOR
REGISTERS
LDFR
LDPE
LDPR
LDCNF
PROGRAM
COUNTER
PGSETR
GETPG
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| ST52513K3 | MAX 3000A CPLD 64 MC 100-TQFP |
| ST52513Y2 | MAX 3000A CPLD 256 MC 256-FBGA |
| ST52513Y3 | MAX II CPLD 570 LE 256-FBGA |
| ST52514F1 | MAX II CPLD 570 LE 100-TQFP |
| ST52514F3 | IC MAX 7000 CPLD 128 100-TQFP |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| ST52513K3 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:8-BIT ICU WITH 10-BIT ADC. TWO TIMERS/PWM. I2C. SPI. SCI. UP TO 8K FLASH |
| ST52513Y2 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:8-BIT ICU WITH 10-BIT ADC. TWO TIMERS/PWM. I2C. SPI. SCI. UP TO 8K FLASH |
| ST52513Y3 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:8-BIT ICU WITH 10-BIT ADC. TWO TIMERS/PWM. I2C. SPI. SCI. UP TO 8K FLASH |
| ST52514F1 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:8-BIT ICU WITH 10-BIT ADC. TWO TIMERS/PWM. I2C. SPI. SCI. UP TO 8K FLASH |
| ST52514F3 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:8-BIT ICU WITH 10-BIT ADC. TWO TIMERS/PWM. I2C. SPI. SCI. UP TO 8K FLASH |
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