參數(shù)資料
型號: ST52513K2
英文描述: MAX 3000A CPLD 32 MC 44-PLCC
中文描述: 8位重癥監(jiān)護(hù)病房,10位ADC。兩個定時器/脈寬調(diào)制。 I2C總線。的SPI。脊髓損傷。提供了8K閃存
文件頁數(shù): 75/106頁
文件大小: 1355K
代理商: ST52513K2
70/106
11.3.1 Simultaneous Start. The
PWM/Timers
can be started simultaneously when working in
PWM mode. The T0SYNC and T1SYNC bits in
PWM0_CR3 Configuration Registers mask the
reset of each timer; after enabling each single
PWM/Timer. They are started by putting off the
mask with a single writing in the PWM0_CR3
Register.
Simultaneous start is also possible in Timer mode.
The timers start counting simultaneously, but the
output pulses are generated according to the
modality configured (square or pulse mode).
11.4 Timer Interrupts
The PWM/Timer can be programmed to generate
an Interrupt Request, both on the falling and the
rising of the TxOUT signal and when there’s a
STOP signal (external or internal). The PWM/
TIMER 1, when the IR Driver is active, can be
configured to generate the IR interrupt (see below),
excluding the other possible sources.
By using the TxIES, TxIER and TxIEF bits of the
Configuration Registers PWMx_CR1, the interrupt
sources can be switched on/off. All the interrupt
sources may be activated at the same time:
sources can be distinguished by reading the
PWMx_STATUS Input Register.
The interrupt on the falling edge corresponds to
half of a counting period in Timer mode when the
waveform is set to Square Wave and to the end of
the Ton phase in PWM mode.
Note: when the PWM Counter is set to 0 or 65535,
the interrupt occurs at the end of each control
period.
In order to be active, the PWM/Timers interrupts
must be enabled by writing the Interrupt Mask
Register
(INT_MASK)
in
the
Configuration
Register Space, bits MSKT0 And MSKT1.
Figure 11.5 PWM/Timers Output Modulation Architecture
FROM PWM/TIMER 0
PWM_LU_CR (0)
PWM_LU_CR (1)
7
6
5
4
3
2
1
0
MUX_LU
FROM IR DRIVER
PWM_LU_CR (4:0)
PWM_LU_CR (5)
T1OUT
FROM PWM/TIMER 1
PWM/TIMER 0
PWM/TIMER 1
CONFIGURATION
REGISTERS
T0OUT
T1OUT
IR DRIVER
LOGIC UNIT
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