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參數(shù)資料
| 型號： | ST52513K2 |
| 英文描述： | MAX 3000A CPLD 32 MC 44-PLCC |
| 中文描述： | 8位重癥監(jiān)護病房，10位ADC。兩個定時器/脈寬調制。 I2C總線。的SPI。脊髓損傷。提供了8K閃存 |
| 文件頁數(shù)： | 93/106頁 |
| 文件大?。?/td> | 1355K |
| 代理商： | ST52513K2 |
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Note: In 10-bit addressing mode, the comparison
includes the header sequence (11110xx0) and the
two most significant bits of the address.
Header matched (10-bit mode only): the interface
generates an acknowledgement pulse if the ACK
bit is set.
Address not matched: the interface ignores it and
waits for another Start condition.
Address matched: the interface generates in
sequence:
– Acknowledge pulse if the ACK bit is set.
– EVF and ADSL bits are set with an interrupt if the
ITE bit is set.
Afterwards, the interface waits for the I2C_SR1
register to be read, holding the SCL line low (see
Figure 13.3 Transfer sequencing EV1).
Next, in 7-bit mode read the I2C_IN register to
determine from the least significant bit (Data
Direction Bit) if the slave must enter Receiver or
Transmitter mode.
In 10-bit mode, after receiving the address
sequence the slave is always in receive mode. It
will enter transmit mode on receiving a repeated
Start condition followed by the header sequence
with matching address bits and the least significant
bit set (11110xx1).
Slave Receiver
Following reception of the address and after the
I2C_SR1 register has been read, the slave
receives bytes from the SDA line into the I2C_IN
register via the internal shift register. After each
byte, the interface generates the following in
sequence:
– Acknowledge pulse if the ACK bit is set
– EVF and BTF bits are set with an interrupt if the
ITE bit is set.
Afterwards, the interface waits for the I2C_SR1
register to be read followed by a read of the I2C_IN
register, holding the SCL line low (see Figure
13.3 Transfer sequencing EV2).
Slave Transmitter
Following the address reception and after the
I2C_SR1 register has been read, the slave sends
bytes from the I2C_OUT register to the SDA line
via the internal shift register.
The slave waits for a read of the I2C_SR1 register
followed by a write in the I2C_OUT register,
holding the SCL line low (see Figure 13.3
Transfer sequencing EV3).
When the acknowledge pulse is received:
– The EVF and BTF bits are set by hardware with
an interrupt if the ITE bit is set.
Closing slave communication
After the last data byte is transferred a Stop
Condition is generated by the master. The
interface detects this condition and sets:
– EVF and STOPF bits with an interrupt if the ITE
bit is set.
Afterwards, the interface waits for a read of the
I2C_SR2 register (see Figure 13.3 Transfer
sequencing EV4).
Error Cases
– BERR: Detection of a Stop or a Start condition
during a byte transfer. In this case, the EVF and
the BERR bits are set with an interrupt if the ITE
bit is set.
If it is a Stop then the interface discards the data,
released the lines and waits for another Start
condition.
If it is a Start then the interface discards the data
and waits for the next slave address on the bus.
– AF: Detection of a non-acknowledge bit. In this
case, the EVF and AF bits are set with an inter-
rupt if the ITE bit is set.
Note: In both cases, the SCL line is not held low;
however, SDA line can remain low due to possible
0 bits transmitted last. At this point, both lines
must be released by software.
How to release the SDA / SCL lines
Set and subsequently clear the STOP bit while
BTF is set. The SDA/SCL lines are released after
the current byte is transferred.
13.4.2 Master Mode.
To switch from default Slave mode to Master mode
a Start condition generation is needed.
Start condition
Setting the START bit while the BUSY bit is
cleared causes the interface to switch to Master
mode (M/SL bit set) and generates a Start
condition.
Once the Start condition is sent:
– The EVF and SB bits are set by hardware with
an interrupt if the ITE bit is set.
Afterwards, the master waits for a read of the
I2C_SR1 register followed by a write in the
I2C_OUT register with the Slave address, holding
the SCL line low (see Figure 13.3 Transfer
sequencing EV5).
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相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| ST52513K3 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:8-BIT ICU WITH 10-BIT ADC. TWO TIMERS/PWM. I2C. SPI. SCI. UP TO 8K FLASH |
| ST52513Y2 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:8-BIT ICU WITH 10-BIT ADC. TWO TIMERS/PWM. I2C. SPI. SCI. UP TO 8K FLASH |
| ST52513Y3 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:8-BIT ICU WITH 10-BIT ADC. TWO TIMERS/PWM. I2C. SPI. SCI. UP TO 8K FLASH |
| ST52514F1 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:8-BIT ICU WITH 10-BIT ADC. TWO TIMERS/PWM. I2C. SPI. SCI. UP TO 8K FLASH |
| ST52514F3 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:8-BIT ICU WITH 10-BIT ADC. TWO TIMERS/PWM. I2C. SPI. SCI. UP TO 8K FLASH |
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