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參數(shù)資料
| 型號： | SN74ABT182502A |
| 廠商： | Texas Instruments, Inc. |
| 英文描述： | Scan Test Devices With 18-Bit Universal Bus Transceivers(掃描測試裝置(帶18位通用總線收發(fā)器)) |
| 中文描述： | 掃描測試設(shè)備與18位通用總線收發(fā)器（掃描測試裝置（帶18位通用總線收發(fā)器）） |
| 文件頁數(shù)： | 8/35頁 |
| 文件大?。?/td> | 738K |
| 代理商： | SN74ABT182502A |
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SN54ABT18502A, SN54ABT182502A, SN74ABT18502A, SN74ABT182502A
SCAN TEST DEVICES WITH
18-BIT UNIVERSAL BUS TRANSCEIVERS
SCBS488 – AUGUST 1994
8
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
Shift-DR (continued)
While in the stable Shift-DR state, data is serially shifted through the selected data register on each TCK cycle.
The first shift occurs on the first rising edge of TCK after entry to the Shift-DR state (i.e., no shifting occurs during
the TCK cycle in which the TAP controller changes from Capture-DR to Shift-DR or from Exit2-DR to Shift-DR).
The last shift occurs on the rising edge of TCK upon which the TAP controller exits the Shift-DR state.
Exit1-DR, Exit2-DR
The
Exit1-DR and Exit2-DR states are temporary states that end a data register scan. It is possible to return
to the Shift-DR state from either Exit1-DR or Exit2-DR without recapturing the data register. On the first falling
edge of TCK after entry to Exit1-DR, TDO goes from the active state to the high-impedance state.
Pause-DR
No specific function is performed in the stable Pause-DR state, in which the TAP controller can remain
indefinitely. The Pause-DR state can suspend and resume data register scan operations without loss of data.
Update-DR
If the current instruction calls for the selected data register to be updated with current data, such update occurs
on the falling edge of TCK following entry to the Update-DR state.
Capture-IR
When an instruction register scan is selected, the TAP controller must pass through the Capture-IR state. In the
Capture-IR state, the instruction register captures its current status value. This capture operation occurs on the
rising edge of TCK upon which the TAP controller exits the Capture-IR state. For the
′
ABT18502A and
′
ABT182502A, the status value loaded in the Capture-IR state is the fixed binary value 10000001.
Shift-IR
Upon entry to the Shift-IR state, the instruction register is placed in the scan path between TDI and TDO, and
on the first falling edge of TCK, TDO goes from the high-impedance state to the active state. TDO enables to
the logic level present in the least significant bit of the instruction register.
While in the stable Shift-IR state, instruction data is serially shifted through the instruction register on each TCK
cycle. The first shift occurs on the first rising edge of TCK after entry to the Shift-IR state (i.e., no shifting occurs
during the TCK cycle in which the TAP controller changes from Capture-IR to Shift-IR or from Exit2-IR to
Shift-IR). The last shift occurs on the rising edge of TCK upon which the TAP controller exits the Shift-IR state.
Exit1-IR, Exit2-IR
The
Exit1-IR and Exit2-IR states are temporary states that end an instruction register scan. It is possible to return
to the Shift-IR state from either Exit1-IR or Exit2-IR without recapturing the instruction register. On the first falling
edge of TCK after entry to Exit1-IR, TDO goes from the active state to the high-impedance state.
Pause-IR
No specific function is performed in the stable Pause-IR state, in which the TAP controller can remain indefinitely.
The Pause-IR state can suspend and resume instruction register scan operations without loss of data.
Update-IR
The current instruction is updated and takes effect on the falling edge of TCK following entry to the Update-IR
state.
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相關(guān)PDF資料 |
PDF描述 |
|---|---|
| SN74ABT18502A | Scan Test Devices With 18-Bit Universal Bus Transceivers(掃描測試裝置(帶18位通用總線收發(fā)器)) |
| SN54ABT182502A | Scan Test Devices With 18-Bit Universal Bus Transceivers(掃描測試裝置(帶18位通用總線收發(fā)器)) |
| SN54ABT18502A | Scan Test Devices With 18-Bit Universal Bus Transceivers(掃描測試裝置(帶18位通用總線收發(fā)器)) |
| SN74AHC16245 | 16-Bit Bus Transceivers With 3-State Outputs(16位緩沖器/驅(qū)動器(三態(tài)輸出)) |
| SN74AHC240DBRG4 | OCTAL BUFFERS/DRIVERS WITH 3-STATE OUTPUTS |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| SN74ABT18502 | 制造商:TI 制造商全稱:Texas Instruments 功能描述:SCAN TEST DEVICE WITH 18-BIT REGISTERED BUS TRANSCEIVER |
| SN74ABT18502_06 | 制造商:TI 制造商全稱:Texas Instruments 功能描述:SCAN TEST DEVICE WITH 18-BIT REGISTERED BUS TRANSCEIVER |
| SN74ABT18502PM | 功能描述:特定功能邏輯 W/18-Bit Univ Bus Trncvr RoHS:否 制造商:Texas Instruments 產(chǎn)品: 系列:SN74ABTH18502A 工作電源電壓:5 V 封裝 / 箱體:LQFP-64 封裝:Tube |
| SN74ABT18502PMG4 | 功能描述:特定功能邏輯 W/18-Bit Univ Bus Trncvr RoHS:否 制造商:Texas Instruments 產(chǎn)品: 系列:SN74ABTH18502A 工作電源電壓:5 V 封裝 / 箱體:LQFP-64 封裝:Tube |
| SN74ABT18502PMR | 功能描述:特定功能邏輯 W/18-Bit Univ Bus Trncvr RoHS:否 制造商:Texas Instruments 產(chǎn)品: 系列:SN74ABTH18502A 工作電源電壓:5 V 封裝 / 箱體:LQFP-64 封裝:Tube |
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