- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄372164 > SN74ABT182502A (Texas Instruments, Inc.) Scan Test Devices With 18-Bit Universal Bus Transceivers(掃描測試裝置(帶18位通用總線收發(fā)器)) PDF資料下載
參數(shù)資料
| 型號： | SN74ABT182502A |
| 廠商： | Texas Instruments, Inc. |
| 英文描述： | Scan Test Devices With 18-Bit Universal Bus Transceivers(掃描測試裝置(帶18位通用總線收發(fā)器)) |
| 中文描述： | 掃描測試設(shè)備與18位通用總線收發(fā)器（掃描測試裝置（帶18位通用總線收發(fā)器）） |
| 文件頁數(shù)： | 24/35頁 |
| 文件大小： | 738K |
| 代理商： | SN74ABT182502A |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁當前第24頁第25頁第26頁第27頁第28頁第29頁第30頁第31頁第32頁第33頁第34頁第35頁
SN54ABT18502A, SN54ABT182502A, SN74ABT18502A, SN74ABT182502A
SCAN TEST DEVICES WITH
18-BIT UNIVERSAL BUS TRANSCEIVERS
SCBS488 – AUGUST 1994
24
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
timing description
All test operations of the
′
ABT18502A and
′
ABT182502A are synchronous to the TCK signal. Data on the TDI,
TMS, and normal-function inputs is captured on the rising edge of TCK. Data appears on the TDO and
normal-function output pins on the falling edge of TCK. The TAP controller is advanced through its states (as
illustrated in Figure 1) by changing the value of TMS on the falling edge of TCK and then applying a rising edge
to TCK.
A simple timing example is illustrated in Figure 13. In this example, the TAP controller begins in the
Test-Logic-Reset state and is advanced through its states as necessary to perform one instruction register scan
and one data register scan. While in the Shift-IR and Shift-DR states, TDI is used to input serial data, and TDO
is used to output serial data. The TAP controller is then returned to the Test-Logic-Reset state. Table 5 explains
the operation of the test circuitry during each TCK cycle.
Table 5. Explanation of Timing Example
TCK
CYCLE(S)
TAP STATE
AFTER TCK
DESCRIPTION
1
Test-Logic-Reset
TMS is changed to a logic 0 value on the falling edge of TCK to begin advancing the TAP controller toward
the desired state.
2
Run-Test/Idle
3
Select-DR-Scan
4
Select-IR-Scan
5
Capture-IR
The IR captures the 8-bit binary value 10000001 on the rising edge of TCK as the TAP controller exits the
Capture-IR state.
6
Shift-IR
TDO becomes active and TDI is made valid on the falling edge of TCK. The first bit is shifted into the TAP on
the rising edge of TCK as the TAP controller advances to the next state.
7–13
Shift-IR
One bit is shifted into the IR on each TCK rising edge. With TDI held at a logic 1 value, the 8-bit binary value
11111111 is serially scanned into the IR. At the same time, the 8-bit binary value 10000001 is serially scanned
out of the IR via TDO. In TCK cycle 13, TMS is changed to a logic 1 value to end the IR scan on the next TCK
cycle. The last bit of the instruction is shifted as the TAP controller advances from Shift-IR to Exit1-IR.
14
Exit1-IR
TDO becomes inactive (goes to the high-impedance state) on the falling edge of TCK.
15
Update-IR
The IR is updated with the new instruction (BYPASS) on the falling edge of TCK.
16
Select-DR-Scan
17
Capture-DR
The bypass register captures a logic 0 value on the rising edge of TCK as the TAP controller exits the
Capture-DR state.
18
Shift-DR
TDO becomes active and TDI is made valid on the falling edge of TCK. The first bit is shifted into the TAP on
the rising edge of TCK as the TAP controller advances to the next state.
19–20
Shift-DR
The binary value 101 is shifted in via TDI, while the binary value 010 is shifted out via TDO.
21
Exit1-DR
TDO becomes inactive (goes to the high-impedance state) on the falling edge of TCK.
22
Update-DR
In general, the selected data register is updated with the new data on the falling edge of TCK.
23
Select-DR-Scan
24
Select-IR-Scan
25
Test-Logic-Reset
Test operation completed
P
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| SN74ABT18502A | Scan Test Devices With 18-Bit Universal Bus Transceivers(掃描測試裝置(帶18位通用總線收發(fā)器)) |
| SN54ABT182502A | Scan Test Devices With 18-Bit Universal Bus Transceivers(掃描測試裝置(帶18位通用總線收發(fā)器)) |
| SN54ABT18502A | Scan Test Devices With 18-Bit Universal Bus Transceivers(掃描測試裝置(帶18位通用總線收發(fā)器)) |
| SN74AHC16245 | 16-Bit Bus Transceivers With 3-State Outputs(16位緩沖器/驅(qū)動器(三態(tài)輸出)) |
| SN74AHC240DBRG4 | OCTAL BUFFERS/DRIVERS WITH 3-STATE OUTPUTS |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| SN74ABT18502 | 制造商:TI 制造商全稱:Texas Instruments 功能描述:SCAN TEST DEVICE WITH 18-BIT REGISTERED BUS TRANSCEIVER |
| SN74ABT18502_06 | 制造商:TI 制造商全稱:Texas Instruments 功能描述:SCAN TEST DEVICE WITH 18-BIT REGISTERED BUS TRANSCEIVER |
| SN74ABT18502PM | 功能描述:特定功能邏輯 W/18-Bit Univ Bus Trncvr RoHS:否 制造商:Texas Instruments 產(chǎn)品: 系列:SN74ABTH18502A 工作電源電壓:5 V 封裝 / 箱體:LQFP-64 封裝:Tube |
| SN74ABT18502PMG4 | 功能描述:特定功能邏輯 W/18-Bit Univ Bus Trncvr RoHS:否 制造商:Texas Instruments 產(chǎn)品: 系列:SN74ABTH18502A 工作電源電壓:5 V 封裝 / 箱體:LQFP-64 封裝:Tube |
| SN74ABT18502PMR | 功能描述:特定功能邏輯 W/18-Bit Univ Bus Trncvr RoHS:否 制造商:Texas Instruments 產(chǎn)品: 系列:SN74ABTH18502A 工作電源電壓:5 V 封裝 / 箱體:LQFP-64 封裝:Tube |
發(fā)布緊急采購，3分鐘左右您將得到回復。