參數(shù)資料
型號： SMJ320C6414DGADW60
廠商： TEXAS INSTRUMENTS INC
元件分類： 數(shù)字信號處理
英文描述： 64-BIT, 75 MHz, OTHER DSP, CPGA570
封裝： 33 X 33 MM, CERAMIC, FCPGA-570
文件頁數(shù)： 82/134頁
文件大?。?/td> 1997K
代理商： SMJ320C6414DGADW60
SMJ320C6414, SMJ320C6415, SMJ320C6416
FIXEDPOINT DIGITAL SIGNAL PROCESSORS
SGUS050A JANUARY 2004 REVISED MARCH 2004
51
POST OFFICE BOX 1443
HOUSTON, TEXAS 772511443
Terminal Functions (Continued)
SIGNAL
TYPE
IPD/
DESCRIPTION
NAME
NO.
TYPE
IPD/
IPU
DESCRIPTION
MULTICHANNEL BUFFERED SERIAL PORT 1 (McBSP1)
CLKS1/
URADDR3§
Y8
I
McBSP1 external clock source (as opposed to internal) (I) [default] or UTOPIA receive
address 3 pin (I)
CLKR1/
URADDR2§
AB7
I/O/Z
McBSP1 receive clock (I/O/Z) [default] or UTOPIA receive address 2 pin (I)
CLKX1/
URADDR4§
T12
I/O/Z
McBSP1 transmit clock (I/O/Z) [default] or UTOPIA receive address 4 pin (I)
DR1/
UXADDR1§
V11
I
McBSP1 receive data (I) [default] or UTOPIA transmit address 1 pin (I)
DX1/
UXADDR4§
Y10
I/O/Z
McBSP1 transmit data (O/Z) [default] or UTOPIA transmit address 4 pin (I)
FSR1/
UXADDR2§
AA8
I/O/Z
McBSP1 receive frame sync (I/O/Z) [default] or UTOPIA transmit address 2 pin (I)
FSX1/
UXADDR3§
AA11
I/O/Z
McBSP1 transmit frame sync (I/O/Z) [default] or UTOPIA transmit address 3 pin (I)
MULTICHANNEL BUFFERED SERIAL PORT 0 (McBSP0)
CLKS0
F4
I
IPD
McBSP0 external clock source (as opposed to internal)
CLKR0
F5
I/O/Z
IPD
McBSP0 receive clock
CLKX0
K9
I/O/Z
IPD
McBSP0 transmit clock
DR0
G6
I
IPU
McBSP0 receive data
DX0
E4
O/Z
IPU
McBSP0 transmit data
FSR0
D3
I/O/Z
IPD
McBSP0 receive frame sync
FSX0
H7
I/O/Z
IPD
McBSP0 transmit frame sync
TIMER 2
TOUT2
F7
O/Z
IPD
Timer 2 or general-purpose output
TINP2
D5
I
IPD
Timer 2 or general-purpose input
TIMER 1
TOUT1
G8
O/Z
IPD
Timer 1 or general-purpose output
TINP1
D6
I
IPD
Timer 1 or general-purpose input
TIMER 0
TOUT0
O/Z
IPD
Timer 0 or general-purpose output
TINP0
E7
I
IPD
Timer 0 or general-purpose input
I = Input, O = Output, Z = High impedance, S = Supply voltage, GND = Ground
IPD = Internal pulldown, IPU = Internal pullup. (These IPD/IPU signal pins feature a 30-k IPD or IPU resistor. To pull up a signal to the opposite
supply rail, a 1-k
resistor should be used.)
§ For the C6415 and C6416 devices, these pins are multiplexed pins. For more details, see the Device Configurations section of this data sheet.
The C6414 device does not support the PCI or UTOPIA peripherals; therefore, these MUXed peripheral pins are standalone peripheral functions
for this device.
相關(guān)PDF資料
PDF描述
SM320C6414DGADW60 64-BIT, 75 MHz, OTHER DSP, CPGA570
SM320C6416DGADW60 64-BIT, 75 MHz, OTHER DSP, CPGA570
SMJ320C6701GLPW16 32-BIT, 166.66 MHz, OTHER DSP, CBGA429
SMJ34010-50FDM GRAPHICS PROCESSOR, CQCC68
SMJ34010-40GBM GRAPHICS PROCESSOR, CPGA68
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