參數(shù)資料
型號： SMJ320C6414DGADW60
廠商： TEXAS INSTRUMENTS INC
元件分類： 數(shù)字信號處理
英文描述： 64-BIT, 75 MHz, OTHER DSP, CPGA570
封裝： 33 X 33 MM, CERAMIC, FCPGA-570
文件頁數(shù)： 11/134頁
文件大?。?/td> 1997K
代理商： SMJ320C6414DGADW60
SMJ320C6414, SMJ320C6415, SMJ320C6416
FIXEDPOINT DIGITAL SIGNAL PROCESSORS
SGUS050A JANUARY 2004 REVISED MARCH 2004
108
POST OFFICE BOX 1443
HOUSTON, TEXAS 772511443
HOST-PORT INTERFACE (HPI) TIMING
timing requirements for host-port interface cycles (see Figure 39 through Figure 46)
NO.
MIN
MAX
UNIT
1
tsu(SELV-HSTBL)
Setup time, select signals§ valid before HSTROBE low
5
ns
2
th(HSTBL-SELV)
Hold time, select signals§ valid after HSTROBE low
2.4
ns
3
tw(HSTBL)
Pulse duration, HSTROBE low
4P*
ns
4
tw(HSTBH)
Pulse duration, HSTROBE high between consecutive accesses
4P*
ns
10
tsu(SELV-HASL)
Setup time, select signals§ valid before HAS low
5
ns
11
th(HASL-SELV)
Hold time, select signals§ valid after HAS low
2
ns
12
tsu(HDV-HSTBH)
Setup time, host data valid before HSTROBE high
5
ns
13
th(HSTBH-HDV)
Hold time, host data valid after HSTROBE high
2.8
ns
14
th(HRDYL-HSTBL)
Hold time, HSTROBE low after HRDY low. HSTROBE should not be
inactivated until HRDY is active (low); otherwise, HPI writes will not complete
properly.
2*
ns
18
tsu(HASL-HSTBL)
Setup time, HAS low before HSTROBE low
2
ns
19
th(HSTBL-HASL)
Hold time, HAS low after HSTROBE low
2.1
ns
*This parameter is not production tested.
HSTROBE refers to the following logical operation on HCS, HDS1, and HDS2: [NOT(HDS1 XOR HDS2)] OR HCS.
P = 1/CPU clock frequency in ns. For example, when running parts at 600 MHz, use P = 1.67 ns.
§ Select signals include: HCNTL[1:0] and HR/W. For HPI16 mode only, select signals also include HHWIL.
Select the parameter value of 4P or 12.5 ns, whichever is greater.
switching characteristics over recommended operating conditions during host-port interface
cycles (see Figure 39 through Figure 46)
NO.
PARAMETER
MIN
MAX
UNIT
6
td(HSTBL-HRDYH) Delay time, HSTROBE low to HRDY high#
1.3
4P + 8
ns
7
td(HSTBL-HDLZ)
Delay time, HSTROBE low to HD low impedance for an
HPI read
2*
ns
8
td(HDV-HRDYL) Delay time, HD valid to HRDY low
3
ns
9
toh(HSTBH-HDV) Output hold time, HD valid after HSTROBE high
1.5
ns
15
td(HSTBH-HDHZ) Delay time, HSTROBE high to HD high impedance
12*
ns
16
td(HSTBL-HDV) Delay time, HSTROBE low to HD valid (HPI16 only)
4P + 8
ns
*This parameter is not production tested.
HSTROBE refers to the following logical operation on HCS, HDS1, and HDS2: [NOT(HDS1 XOR HDS2)] OR HCS.
P = 1/CPU clock frequency in ns. For example, when running parts at 600 MHz, use P = 1.67 ns.
# This parameter is used during HPID reads and writes. For reads, at the beginning of a word transfer (HPI32) or the first half-word transfer (HPI16)
on the falling edge of HSTROBE, the HPI sends the request to the EDMA internal address generation hardware, and HRDY remains high until
the EDMA internal address generation hardware loads the requested data into HPID. For writes, HRDY goes high if the internal write buffer is
full.
相關PDF資料
PDF描述
SM320C6414DGADW60 64-BIT, 75 MHz, OTHER DSP, CPGA570
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