參數(shù)資料
型號: SMJ320C6414DGADW60
廠商: TEXAS INSTRUMENTS INC
元件分類: 數(shù)字信號處理
英文描述: 64-BIT, 75 MHz, OTHER DSP, CPGA570
封裝: 33 X 33 MM, CERAMIC, FCPGA-570
文件頁數(shù): 114/134頁
文件大?。?/td> 1997K
代理商: SMJ320C6414DGADW60
SMJ320C6414, SMJ320C6415, SMJ320C6416
FIXEDPOINT DIGITAL SIGNAL PROCESSORS
SGUS050A JANUARY 2004 REVISED MARCH 2004
80
POST OFFICE BOX 1443
HOUSTON, TEXAS 772511443
INPUT AND OUTPUT CLOCKS
timing requirements for CLKIN§ (see Figure 16)
NO.
PLL MODE x12
PLL MODE x6
x1 (BYPASS)
UNIT
NO.
MIN
MAX
MIN
MAX
MIN
MAX
UNIT
1
tc(CLKIN)
Cycle time, CLKIN
20
33.3
13.3
33.3
13.3*
33.3
ns
2
tw(CLKINH) Pulse duration, CLKIN high
0.4C*
0.45C*
ns
3
tw(CLKINL)
Pulse duration, CLKIN low
0.4C*
0.45C*
ns
4
tt(CLKIN)
Transition time, CLKIN
5*
1*
ns
*This parameter is not production tested.
The reference points for the rise and fall transitions are measured at VIL MAX and VIH MIN.
For more details on the PLL multiplier factors (x6, x12), see the Clock PLL section of this data sheet.
§ C = CLKIN cycle time in ns. For example, when CLKIN frequency is 50 MHz, use C = 20 ns.
CLKIN
1
2
3
4
Figure 16. CLKIN Timing
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