參數(shù)資料
型號: SMJ320C6414DGADW60
廠商: TEXAS INSTRUMENTS INC
元件分類: 數(shù)字信號處理
英文描述: 64-BIT, 75 MHz, OTHER DSP, CPGA570
封裝: 33 X 33 MM, CERAMIC, FCPGA-570
文件頁數(shù): 23/134頁
文件大?。?/td> 1997K
代理商: SMJ320C6414DGADW60
SMJ320C6414, SMJ320C6415, SMJ320C6416
FIXEDPOINT DIGITAL SIGNAL PROCESSORS
SGUS050A JANUARY 2004 REVISED MARCH 2004
119
POST OFFICE BOX 1443
HOUSTON, TEXAS 772511443
MULTICHANNEL BUFFERED SERIAL PORT (McBSP) TIMING (CONTINUED)
timing requirements for FSR when GSYNC = 1 (see Figure 52)
NO.
MIN
MAX
UNIT
1
tsu(FRH-CKSH) Setup time, FSR high before CLKS high
4*
ns
2
th(CKSH-FRH)
Hold time, FSR high after CLKS high
4*
ns
*This parameter is not production tested.
2
1
CLKS
FSR external
CLKR/X (no need to resync)
CLKR/X (needs resync)
Figure 52. FSR Timing When GSYNC = 1
timing requirements for McBSP as SPI Master or Slave: CLKSTP = 10b, CLKXP = 0 (see Figure 53)
NO.
MASTER
SLAVE
UNIT
NO.
MIN
MAX
MIN
MAX
UNIT
4
tsu(DRV-CKXL)
Setup time, DR valid before CLKX low
12
2 12P
ns
5
th(CKXL-DRV)
Hold time, DR valid after CLKX low
4
5 + 24P
ns
P = 1/CPU clock frequency in ns. For example, when running parts at 600 MHz, use P = 1.67 ns.
For all SPI Slave modes, CLKG is programmed as 1/4 of the CPU clock by setting CLKSM = CLKGDV = 1.
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