參數(shù)資料
型號(hào): SMJ320C6414DGADW60
廠商: TEXAS INSTRUMENTS INC
元件分類: 數(shù)字信號(hào)處理
英文描述: 64-BIT, 75 MHz, OTHER DSP, CPGA570
封裝: 33 X 33 MM, CERAMIC, FCPGA-570
文件頁數(shù): 117/134頁
文件大?。?/td> 1997K
代理商: SMJ320C6414DGADW60
SMJ320C6414, SMJ320C6415, SMJ320C6416
FIXEDPOINT DIGITAL SIGNAL PROCESSORS
SGUS050A JANUARY 2004 REVISED MARCH 2004
83
POST OFFICE BOX 1443
HOUSTON, TEXAS 772511443
INPUT AND OUTPUT CLOCKS (CONTINUED)
Ideal Clock Period
1
5
6
2
3
ECLKIN
ECLKOUT1
4
Figure 20. ECLKOUT1 Timing for EMIFA and EMIFB Modules
switching characteristics over recommended operating conditions for ECLKOUT2 for the EMIFA
and EMIFB modules§ (see Figure 21)
NO.
PARAMETER
MIN
MAX
UNIT
1
tJ(EKO2)
Period jitter, ECLKOUT2
0*
±175*
ps
2
tw(EKO2H)
Pulse duration, ECLKOUT2 high
0.5NE 0.7*
0.5NE + 0.7*
ns
3
tw(EKO2L)
Pulse duration, ECLKOUT2 low
0.5NE 0.7*
0.5NE + 0.7*
ns
4
tt(EKO2)
Transition time, ECLKOUT2
1*
ns
5
td(EKIH-EKO2H) Delay time, ECLKIN high to ECLKOUT2 high
1*
8*
ns
6
td(EKIH-EKO2L) Delay time, ECLKIN high to ECLKOUT2 low
1*
8*
ns
*This parameter is not production tested.
The reference points for the rise and fall transitions are measured at VOL MAX and VOH MIN.
These C64x devices have two EMIFs (64-bit EMIFA and 16-bit EMIFB). All EMIFA signals are prefixed by an “A” and all EMIFB signals are
prefixed by a “B”. Throughout the rest of this document, in generic EMIF areas of discussion, the prefix “A” or “B” may be omitted.
§ E = the EMIF input clock (ECLKIN, CPU/4 clock, or CPU/6 clock) period in ns for EMIFA or EMIFB.
N = the EMIF input clock divider; N = 1, 2, or 4.
This period jitter specification was measured with CPU/4 or CPU/6 as the source of the EMIF input clock.
Ideal Clock Period
5
6
ECLKIN
ECLKOUT2
4
1
2
3
Figure 21. ECLKOUT2 Timing for the EMIFA and EMIFB Modules
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