參數(shù)資料
型號(hào)： SME5434PCI-440
元件分類(lèi)： 微控制器/微處理器
英文描述： 64-BIT, 440 MHz, RISC PROCESSOR, XMA
封裝： 130 X 100 MM, 45 MM HEIGHT MODULE
文件頁(yè)數(shù)： 8/30頁(yè)
文件大?。?/td> 393K
代理商： SME5434PCI-440
16
SME5431PCI-360
SME5434PCI-440
Preliminary
360/440MHz CPU; 0.25 to 2 MB L2 cache; UPA64S, 66MHz PCI Interfaces
UltraSPARC IIi CPU Module
September 2001
Sun Microsystems, Inc
UltraSPARC-IIi UPA_CLK
UPA_CLK input to the fast-frame-buffer ASIC external to the module
CPU_CLK input to the UltraSPARC-IIi processor
The SRAM_CLK and the CPU_CLK signals to the UltraSPARC-IIi CPU are driven by the same source. The
UPA_CLK signal is (only) used by the UltraSPARC-IIi CPU to set the phase relationship between the CPU
clock and data transfers at the UPA64S interface. Consequently, any timing mismatch between the UPA_CLK
and the CPU_CLK linearly degrades the timing margin to and from the UltraSPARC-IIi and a UPA64S device,
for example an FFB.
Since the CPU_CLK signal is completely contained in the module, once a delay is designed into this module,
system board implementations must match that delay value in the UPA_CLK signal or lose margin by the
amount of the mismatch. Note that the terms UPA_CLK, CPU_CLK, and SRAM_CLK are convenient refer-
ences to the differential signal pairs carried by lines: UPA_CLK_POS and UPA_CLK_NEG, CPU_CLK_POS
and CPU_CLK_NEG, and SRAM_CLK_POS and SRAM_CLK_NEG respectively. See "" on page 7.
Even if traces are perfectly matched, a number of factors cause accumulation of clock skew between the
on-board CPU clock and the UPA_CLK signals—as driven off module. These factors include:
Separate buffers on the module:
± 200 ps
UltraSPARC-IIi and FFB sockets:
± 50 ps
Board fabrication variance:
± 250 ps
Setup/hold/clock input to data-output delay differences:
± 150 ps
System noise:
± 150 ps
When doing a system timing budget, this total skew must be added to the setup, hold, and propagation times
listed for UPA and DRAM signals in the UltraSPARC-IIi CPU component data sheet SME1430LGA [1].
The UPA bus on the module is designed to account for the accumulation of:
6 in of system board trace
3.4 in of FFB trace
setup-time differences between UPA64S interface ASIC and UltraSPARC-IIi CPU that were found from
circuit simulation
These traces are calculated at a delay characteristic of approximately 180 ps/in.
1. Document Part Number: 805-7291-01
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