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參數資料
| 型號： | SME5434PCI-440 |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 64-BIT, 440 MHz, RISC PROCESSOR, XMA |
| 封裝： | 130 X 100 MM, 45 MM HEIGHT MODULE |
| 文件頁數： | 28/30頁 |
| 文件大?。?/td> | 393K |
| 代理商： | SME5434PCI-440 |
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360/440MHz CPU; 0.25 to 2 MB L2 cache; UPA64S, 66MHz PCI Interfaces
UltraSPARC IIi CPU Module
September 2001
Sun Microsystems, Inc
SME5431PCI-360
SME5434PCI-440
Preliminary
All sustained DMA numbers are for a single device. Multiple devices on separate secondary buses can cause
higher sustained bandwidths. In no case is the combined bandwidth from two secondary buses less than the
peak bandwidth available from one bus. This is because of efcient internal arbitration between multiple
events in the bus bridge.
PCI Bandwidth
PCI Sustained Bandwidth (Estimated)
From processor PCI Bus
(DMA) to DRAM
66 MHz, 32-bit
Random 64-byte reads
132 MB/s
Random 64-byte writes
151 MB/s
From processor PCI Bus
(DMA) to L2 cache
66 MHz, 32-bit
Random 64-byte reads
163 MB/s
Random 64-byte writes
186 MB/s
From processor to processor
PCI bus (PIO)
66 MHz, 32-bit
64-byte writes
200 MB/s
UPA64S Bus Bandwidth
UPA PIO Bandwidth (Estimated)
From the CPU to
UPA64S bus (PIO)
360 MHz CPU
90 MHz, 64 bit
Random 64-byte writes
576 MB/s
Compressed 8-byte writes
720 MB/s
440 MHz CPU
110 MHz, 64 bit
Random 64-byte writes
704 MB/s
Compressed 8-byte writes
880 MB/s
PCI Bandwidth with APB (33MHz Secondary Bus)
PCI Secondary Sustained Bandwidth (Estimated)
From the processor, to the
secondary PCI Bus (PIO)
33 MHz, 32-bit
64-byte writes
124 MB/s
From the secondary PCI bus
(DMA) to the DRAM
33 MHz, 32-bit
Random 64-byte reads
78 MB/s
Random 64-byte writes
124 MB/s
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參數描述 |
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