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參數(shù)資料
| 型號： | SME5434PCI-440 |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 64-BIT, 440 MHz, RISC PROCESSOR, XMA |
| 封裝： | 130 X 100 MM, 45 MM HEIGHT MODULE |
| 文件頁數(shù)： | 3/30頁 |
| 文件大?。?/td> | 393K |
| 代理商： | SME5434PCI-440 |
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360/440MHz CPU; 0.25 to 2 MB L2 cache; UPA64S, 66MHz PCI Interfaces
UltraSPARC IIi CPU Module
September 2001
Sun Microsystems, Inc
SME5431PCI-360
SME5434PCI-440
Preliminary
CLOCK DISTRIBUTION
A high-frequency clock signal is generated within the module using a high frequency PLL clock generator
(part number MC12430) from a 16MHz series resonant crystal. The clocks are differential Low Voltage Posi-
tive ECL (LVPECL). The PLL clock generator provides a serial and parallel interface for setting the frequency.
The parallel interface pins are hardwired on the module and their state is loaded during reset. The serial inter-
face signals S_LOAD, S_DATA, and S_CLOCK are brought out to the Memory/UPA64S external connector to
allow frequency setting from the system board.
The high-frequency clock from the clock generator is divided down by a clock divider (part number
MC100LVEL39) to produce the processor and UPA64S clock signals. Only the UPA64S LV PECL clock signal
(at 1/4 of the CPU clock frequency) is a module output. It appears on the 180-pin Memory/UPA64S external
connector.
A clock buffer (part number MC100LVEP210) distributes the HSTL-level clocks to the CPU and SRAM.
Figure 3 shows a schematic diagram of the module clock distribution.
Figure 3. Module Clock Distribution
PCI Clock
UPA64S
f/2
f/4
SRAM
Clock Generator
MC12430
Frequency Divider MC100LVE39
PLL Clock Buffer
UltraSPARC-II
i
Note 1
Note 1: The CPU’s PLL doubles the incoming frequency for the CPU pipeline
Parallel Interface
Serial Interface
Note 2: Multiple HSTL pins connect to the SRAMs
Note 2
CPU
Bus
LVPECL outputs
HSTL outputs
Module boundary
CPU_CLK
SRAM_CLK
UPA_CLK
CPU_CLK
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