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參數(shù)資料
| 型號： | SME5434PCI-440 |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 64-BIT, 440 MHz, RISC PROCESSOR, XMA |
| 封裝： | 130 X 100 MM, 45 MM HEIGHT MODULE |
| 文件頁數(shù)： | 7/30頁 |
| 文件大小： | 393K |
| 代理商： | SME5434PCI-440 |
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360/440MHz CPU; 0.25 to 2 MB L2 cache; UPA64S, 66MHz PCI Interfaces
UltraSPARC IIi CPU Module
September 2001
Sun Microsystems, Inc
SME5431PCI-360
SME5434PCI-440
Preliminary
TIMING SPECIFICATIONS
Timing design within the module makes demands upon signal timing at the module connectors. This section
describes internal module timing when it is useful to explain external requirements. For detailed information
on timing and latencies see Sun publications:
“UltraSPARC–IIi Highly Integrated RISC Processor, PCI Interface.” Data Sheet, SME1430LGA [1]
“UltraSPARC–IIi User’s Manual,” SME1040CGA [2]
PCI
PCI_CLK and PCI_REF_CLK traces on the module are matched in length to within 0.5 in trace length, or
100 ps at a nominal length corresponding to 550 ps. These signals have no added delay and their trace lengths
are also within
± 0.5 in of those of the other PCI signals. Setup, hold and propagation times are listed in the
UltraSPARC-IIi component data sheet, SME1430LGA [1]. See Figure 4.
Figure 4. PCI Clock Trace Delays
DRAM
DRAM signals are all matched to within 0.5 in trace length on the module.
UPA
Within the module design, the following sets of clock signals need to have minimum, ideally zero, skew
between them.
Core Voltage Encoding
Module Pins
VDD_CORE
VID4
VID3
VID2
VID1
VID0
V (DC)
0
1
1.90
1. Document Part Number: 805-7291
2. Document Part Number: 805-0087
PCI_CLK
PCI_REF_CLK
All other PCI signals
L1
L2
L3
L2 = L1
± 100 ps
CPU
L3 = L1
± 100 ps
= 550
± 50 ps
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