參數(shù)資料
型號: SAB-C163-16F25F
廠商: INFINEON TECHNOLOGIES AG
元件分類: 微控制器/微處理器
英文描述: 16-BIT, FLASH, 25 MHz, MICROCONTROLLER, PQFP100
封裝: METRIC, PLASTIC, TQFP-100
文件頁數(shù): 48/66頁
文件大?。?/td> 669K
代理商: SAB-C163-16F25F
1997 Intermediate Version
Semiconductor Group
52
1997-10-01
C163-16F
AC Characteristics
Demultiplexed Bus
V
CC = 5 V ± 10 %;
V
SS = 0 V
T
A = 0 to +70 C
for SAB-C163-16F-LF, SAB-C163-16F-L25F
C
L (for PORT0, PORT1, Port 4, ALE, RD, WR, BHE, CLKOUT) = 100 pF
C
L (for Port 6, CS) = 100 pF
ALE cycle time = 4 TCL + 2
t
A + tC + tF (80 ns at 25 MHz CPU clock without waitstates)
Parameter
Symbol
Max. CPU Clock
= 25 MHz
Variable CPU Clock
1 / 2TCL = 1 to 25 MHz
Unit
min.
max.
min.
max.
ALE high time
t
5
CC 10 +
t
A
TCL - 10
+
t
A
–ns
Address setup to ALE
t
6
CC 4 + t
A
TCL - 16
+
t
A
–ns
ALE falling edge to RD,
WR (with RW-delay)
t
8
CC 10 + t
A
TCL - 10
+
t
A
–ns
ALE falling edge to RD,
WR (no RW-delay)
t
9
CC -10 + t
A
-10
+
t
A
–ns
RD, WR low time
(with RW-delay)
t
12
CC 30 +
t
C
2TCL - 10
+
t
C
–ns
RD, WR low time
(no RW-delay)
t
13
CC 50 +
t
C
3TCL - 10
+
t
C
–ns
RD to valid data in
(with RW-delay)
t
14
SR –
20 +
t
C
2TCL - 20
+
t
C
ns
RD to valid data in
(no RW-delay)
t
15
SR –
40 +
t
C
3TCL - 20
+
t
C
ns
ALE low to valid data in
t
16
SR –
40
+
t
A + tC
3TCL - 20
+
t
A + tC
ns
Address to valid data in
t
17
SR –
50
+2
t
A + tC
4TCL - 30
+2
t
A + tC
ns
Data hold after RD
rising edge
t
18
SR 0
0–ns
Data float after RD rising
edge (with RW-delay 1))
t
20
SR –
26 +
t
F
2TCL - 14
+2
t
A + tF
1)
ns
Data float after RD rising
edge (no RW-delay 1))
t
21
SR –
10 +
t
F
TCL - 10
+2
t
A + tF
1)
ns
Data valid to WR
t
22
CC 20 +
t
C
2TCL - 20
+
t
C
–ns
Data hold after WR
t
24
CC 10 +
t
F
TCL - 10
+
t
F
–ns
相關(guān)PDF資料
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SAB-C165-L25F 16-BIT, 14 MHz, MICROCONTROLLER, PQFP100
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