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| 型號： | SAB-C163-16F25F |
| 廠商： | INFINEON TECHNOLOGIES AG |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 16-BIT, FLASH, 25 MHz, MICROCONTROLLER, PQFP100 |
| 封裝： | METRIC, PLASTIC, TQFP-100 |
| 文件頁數(shù)： | 38/66頁 |
| 文件大?。?/td> | 669K |
| 代理商： | SAB-C163-16F25F |
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1997 Intermediate Version
Semiconductor Group
43
1997-10-01
C163-16F
Phase Locked Loop
For all other combinations of pins P0.15-13 (P0H.7-5) during reset the on-chip phase locked loop is
enabled and provides the CPU clock (see table above). The PLL multiplies the input frequency by
the factor F which is selected via the combination of pins P0.15-13 (i.e. fCPU = fXTAL * F). With every
F’th transition of fXTAL the PLL circuit synchronizes the CPU clock to the input clock. This
synchronization is done smoothely, i.e. the CPU clock frequency does not change abruptly.
Due to this adaptation to the input clock the frequency of fCPU is constantly adjusted so it is locked
to fXTAL. The slight variation causes a jitter of fCPU which also effects the duration of individual TCLs.
The timings listed in the AC Characteristics that refer to TCLs therefore must be calculated using the
minimum TCL that is possible under the respective circumstances.
The actual minimum value for TCL depends on the jitter of the PLL. As the PLL is constantly
adjusting its output frequency so it corresponds to the applied input frequency (crystal or oscillator)
the relative deviation for periods of more than one TCL is lower than for one single TCL (see formula
and figure below).
For a period of
N * TCL the minimum value is computed using the corresponding deviation DN:
TCLmin = TCLNOM * (1 - DN / 100)
DN = ±(4 - N /15) [%],
where
N = number of consecutive TCLs
and 1
≤ N ≤ 40.
So for a period of 3 TCLs (i.e.
N = 3): D3 = 4 - 3/15 = 3.8%,
and (3TCL)min = 3TCLNOM * (1 - 3.8 / 100) = 3TCLNOM * 0.962 (57.72 nsec @ fCPU = 25 MHz).
This is especially important for bus cycles using waitstates and e.g. for the operation of timers, serial
interfaces, etc. For all slower operations and longer periods (e.g. pulse train generation or
measurement, lower baudrates, etc.) the deviation caused by the PLL jitter is neglectible.
Figure 13
Approximated Maximum PLL Jitter
0
1
2
3
4
Max.jitter
N
0
2
4
8
16
32
%
MCD03663
This approximated formula is valid for
1 <
N < 40 and 10 MHz < f CPU < 25 MHz.
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| SAB-C165-L25F | 16-BIT, 14 MHz, MICROCONTROLLER, PQFP100 |
| SAB-C165-R25M | 16-BIT, MROM, 14 MHz, MICROCONTROLLER, PQFP100 |
| SAB-C502-LN | 8-BIT, 12 MHz, MICROCONTROLLER, PQCC44 |
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| SABC16324D33F | 制造商:INFINEON 功能描述:New |
| SABC163L25F | 制造商:Infineon Technologies AG 功能描述:MCU 16-bit C166 CISC/RISC ROMLess 5V 100-Pin TQFP |
| SAB-C163-L25F | 制造商:Rochester Electronics LLC 功能描述:- Bulk |
| SABC163-L25FTR | 制造商:Infineon Technologies AG 功能描述:MCU 16-Bit C166 CISC/RISC ROMLess 5V 100-Pin TQFP T/R |
| SABC163LF | 制造商:Infineon Technologies AG 功能描述:MCU 16-Bit C166 CISC/RISC ROMLess 5V 100-Pin TQFP |
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