參數(shù)資料
型號: SAB-C163-16F25F
廠商: INFINEON TECHNOLOGIES AG
元件分類: 微控制器/微處理器
英文描述: 16-BIT, FLASH, 25 MHz, MICROCONTROLLER, PQFP100
封裝: METRIC, PLASTIC, TQFP-100
文件頁數(shù): 21/66頁
文件大?。?/td> 669K
代理商: SAB-C163-16F25F
1997 Intermediate Version
Semiconductor Group
28
1997-10-01
C163-16F
External Host Mode Programming
In addition to the method described above the C163-16F’s Flash module may also programmed by
external programming devices.
External Host Mode (EHM) is enabled by selecting emulation mode (P0L.0=’0’) and also pulling
low pin P0L.5. Pins P0L.5...0 represent ‘01 1110’ in this case.
In External Host Mode the signals to control a programming cycle are generated by an external host
using the C163-16F’s bus interface. The external host provides the data to be programmed. The
C163-16F itself is switched off and its Flash module can be accessed like standalone memory.
The following port pins represent the interface to the C163-16F’s Flash module in EHM:
The access cycles generated by the external host must fulfill the timing requirements shown in the
timing diagrams above.
Note: EHM is a varity of the emulation mode where pin P0.15 (P0L.7) is inverted during the reset
configuration. This influences the selected clock generation mode.
For EHM operation direct drive or prescaler mode must be configured. If the on-chip
oscillator is not supplied with a clock signal the oscillator watchdog must not be disabled, so
the PLL can provide the clock signal instead.
Signal ALE is used for internal synchronization and for the state machine. Therefore the following
rules must be obeyed:
q
Min. 1 dummy read cycle after each command sequence.
q
Min. 20 dummy read cycles after each program or erase command.
q
Min. 2 dummy read cycles before each read status command.
External Host Mode Interface Signals
Signal
Pin
Description
ADDR
P4.0,
P1H.7 - P1L.1
Physical Flash word address (address line A0 is not evaluated).
DATA
P0H.7 - P0L.0
Word to be written or read
RD
Read cycle control
WR
Programming cycle control
CE
P3.9
Flash enable signal
ALE
Address latch enable (indicates begin of bus cycle and is used
for synchronization)
RSTOUT
Must be held high (pullup resistor)
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