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參數資料
| 型號： | SAB-C163-16F25F |
| 廠商： | INFINEON TECHNOLOGIES AG |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 16-BIT, FLASH, 25 MHz, MICROCONTROLLER, PQFP100 |
| 封裝： | METRIC, PLASTIC, TQFP-100 |
| 文件頁數： | 14/66頁 |
| 文件大?。?/td> | 669K |
| 代理商： | SAB-C163-16F25F |
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1997 Intermediate Version
Semiconductor Group
21
1997-10-01
C163-16F
Watchdog Timer
The Watchdog Timer represents one of the fail-safe mechanisms which have been implemented to
prevent the controller from malfunctioning for longer periods of time.
The Watchdog Timer is always enabled after a reset of the chip, and can only be disabled in the time
interval until the EINIT (end of initialization) instruction has been executed. Thus, the chip’s start-up
procedure is always monitored. The software has to be designed to service the Watchdog Timer
before it overflows. If, due to hardware or software related failures, the software fails to do so, the
Watchdog Timer overflows and generates an internal hardware reset and pulls the RSTOUT pin low
in order to allow external hardware components to be reset.
The Watchdog Timer is a 16-bit timer, clocked with the system clock divided either by 2 or by 128.
The high byte of the Watchdog Timer register can be set to a prespecified reload value (stored in
WDTREL) in order to allow further variation of the monitored time interval. Each time it is serviced
by the application software, the high byte of the Watchdog Timer is reloaded. Thus, time intervals
between 20 s and 336 ms can be monitored (@ 25 MHz). The default Watchdog Timer interval after
reset is 5.24 ms (@ 25 MHz).
Oscillator Watchdog
The Oscillator Watchdog (OWD) monitors the clock signal generated by the on-chip oscillator
(either with a crystal or via external clock drive). For this operation the PLL provides a clock signal
which is used to supervise transitions on the oscillator clock. This PLL clock is independent from the
XTAL1 clock. When the expected oscillator clock transitions are missing the OWD activates the PLL
Unlock / OWD interrupt node and supplies the CPU with the PLL clock signal. Under these
circumstances the PLL will oscillate with its basic frequency.
The oscillator watchdog of the C163-16F can be disabled in two ways:
q
Provide a low level on pin OWE, or
q
Set bit OWDDIS (SYSCON.4).
If either condition is true the on-chip oscillator watchdog is disabled and the CPU clock is always fed
from the oscillator input. After reset the oscillator watchdog is enabled and active.
The operation of the OWD is controlled according to the table below:
Note: The CPU clock source is only switched back to the oscillator clock after a hardware reset.
OWDDIS = ’0’
OWDDIS = ’1’
OWE = ’0’, ie.
VOWE = VIL
Disabled
OWE = ’1’, ie.
VIH ≤ VOWE < 13.2V
OWD active
Disabled
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PDF描述 |
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| SAB-C165-L25F | 16-BIT, 14 MHz, MICROCONTROLLER, PQFP100 |
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| SAB-C502-LN | 8-BIT, 12 MHz, MICROCONTROLLER, PQCC44 |
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相關代理商/技術參數 |
參數描述 |
|---|---|
| SABC16324D33F | 制造商:INFINEON 功能描述:New |
| SABC163L25F | 制造商:Infineon Technologies AG 功能描述:MCU 16-bit C166 CISC/RISC ROMLess 5V 100-Pin TQFP |
| SAB-C163-L25F | 制造商:Rochester Electronics LLC 功能描述:- Bulk |
| SABC163-L25FTR | 制造商:Infineon Technologies AG 功能描述:MCU 16-Bit C166 CISC/RISC ROMLess 5V 100-Pin TQFP T/R |
| SABC163LF | 制造商:Infineon Technologies AG 功能描述:MCU 16-Bit C166 CISC/RISC ROMLess 5V 100-Pin TQFP |
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