參數(shù)資料
型號(hào): SAB-C163-16F25F
廠商: INFINEON TECHNOLOGIES AG
元件分類: 微控制器/微處理器
英文描述: 16-BIT, FLASH, 25 MHz, MICROCONTROLLER, PQFP100
封裝: METRIC, PLASTIC, TQFP-100
文件頁數(shù): 41/66頁
文件大?。?/td> 669K
代理商: SAB-C163-16F25F
1997 Intermediate Version
Semiconductor Group
46
1997-10-01
C163-16F
Data valid to WR
t
22
CC 20 +
t
C
2TCL - 20
+
t
C
–ns
Data hold after WR
t
23
CC 26 +
t
F
2TCL - 14
+
t
F
–ns
ALE rising edge after RD,
WR
t
25
CC 26 +
t
F
2TCL - 14
+
t
F
–ns
Address hold after RD,
WR
t
27
CC 26 +
t
F
2TCL - 14
+
t
F
–ns
ALE falling edge to CS
t
38
CC -4 -
t
A
10 -
t
A
-4 -
t
A
10 -
t
A
ns
CS low to Valid Data In
t
39
SR –
40
+
t
C +2tA
3TCL - 20
+
t
C+2tA
ns
CS hold after RD, WR
t
40
CC 46 +
t
F
3TCL - 14
+
t
F
–ns
ALE fall. edge to RdCS,
WrCS (with RW delay)
t
42
CC 16 +
t
A
TCL - 4
+
t
A
–ns
ALE fall. edge to RdCS,
WrCS (no RW delay)
t
43
CC -4 +
t
A
–-4
+
t
A
–ns
Address float after RdCS,
WrCS (with RW delay)
t
44
CC –
0
–0ns
Address float after RdCS,
WrCS (no RW delay)
t
45
CC –
20
TCL
ns
RdCS to Valid Data In
(with RW delay)
t
46
SR –
16 +
t
C
2TCL - 24
+
t
C
ns
RdCS to Valid Data In
(no RW delay)
t
47
SR –
36 +
t
C
3TCL - 24
+
t
C
ns
RdCS, WrCS Low Time
(with RW delay)
t
48
CC 30 +
t
C
2TCL - 10
+
t
C
–ns
RdCS, WrCS Low Time
(no RW delay)
t
49
CC 50 +
t
C
3TCL - 10
+
t
C
–ns
Data valid to WrCS
t
50
CC 26 +
t
C
2TCL - 14
+
t
C
–ns
Data hold after RdCS
t
51
SR 0
0–ns
Data float after RdCS
t
52
SR –
20 +
t
F
2TCL - 20
+
t
F
ns
Parameter
Symbol
Max. CPU Clock
= 25 MHz
Variable CPU Clock
1 / 2TCL = 1 to 25 MHz
Unit
min.
max.
min.
max.
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