I-52
EPSON
S1C88348/317/316/308 TECHNICAL HARDWARE
5 PERIPHERAL CIRCUITS AND THEIR OPERATION (Oscillation Circuits and Operating Mode)
When crystal oscillation is selected, a crystal
oscillation circuit can be easily formed by connect-
ing a crystal oscillator X'tal1 (Typ. 32.768 kHz)
between the OSC1 and OSC2 terminals along with
a trimmer capacitor CG1 (5–25 pF) between the
OSC1 terminal and VSS.
In addition, the gate capacitor CG1 (5 pF) can be
built into the circuit by the mask option.
When CR oscillation is selected, connect a resistor
(RCR1) between the OSC1 and OSC2 terminals.
When external input is selected, release the OSC2
terminal and input the rectangular wave clock into
the OSC1 terminal.
5.4.4 OSC3 oscillation circuit
The OSC3 oscillation circuit generates the system
clock when the CPU and some peripheral circuits
(output port, serial interface and programmable
timer) are in high speed operation.
This oscillation circuit stops when the SLP instruc-
tion is executed, or the OSCC register is set to "0".
In terms of oscillation circuit types, any one of
crystal oscillation, ceramic oscillation, CR oscilla-
tion or external clock input can be selected with the
mask option.
Figure 5.4.4.1 shows the configuration of the OSC3
oscillation circuit.
When crystal or ceramic oscillation circuit is
selected, the crystal or ceramic oscillation circuit are
formed by connecting either a crystal oscillator
(X'tal2) or a combination of ceramic oscillator
(Ceramic) and feedback resistor (Rf) between OSC3
and OSC4 terminals and connecting two capacitors
(CG2, CD2) between the OSC3 terminal and VSS, and
between the OSC4 terminal and VSS, respectively.
When CR oscillation is selected, the CR oscillation
circuit is formed merely by connecting a resistor
(RCR3) between OSC3 and OSC4 terminals.
When external input is selected, release the OSC4
terminal and input the rectangular wave clock into
the OSC3 terminal.
5.4.5 Operating mode
You can select three types of operating modes using
software, to obtain a stable operation and good
characteristics (operating frequency and current
consumption) over a broad operation voltage. Here
below are indicated the features of the respective
modes.
Normal mode (VDD = 2.4 V–5.5 V)
This mode is set following the initial reset. It
permits the OSC3 oscillation circuit (Max. 4.2
MHz) to be used and also permits relative low
power operation.
Low power mode (VDD = 1.8 V–3.5 V)
This is a lower power mode than the normal
mode. It makes ultra-low power consumption
possible by operation on the OSC1 oscillation
circuit, although the OSC3 circuit cannot be
used.
High speed mode (VDD = 3.5 V–5.5 V)
This mode permits higher speed operation than
the normal mode. Since the OSC3 oscillation
circuit (Max. 8.2 MHz) can be used, you should
use this mode, when you require operation at
4.2 MHz or more. However, the current con-
sumption will increase relative to the normal
mode.
Using software to switch over among the above
three modes to meet your actual usage circum-
stances will make possible a low power system. For
example, you will be able to reduce current con-
sumption by switching over to the normal mode
when using the OSC3 as the CPU clock and,
conversely, changing over to the low power mode
when using the OSC1 as the CPU clock (OSC3
oscillation circuit is OFF).
VSS
OSC4
OSC3
Rf
CD2
CG2
fOSC3
Oscillation circuit
control signal
SLEEP status
X'tal 2
or
Ceramic
Oscillation circuit
control signal
SLEEP status
OSC4
OSC3
RCR3
fOSC3
OSC4
OSC3
External
clock
N.C.
VSS
VDD
fOSC3
Oscillation circuit
control signal
SLEEP status
(1) Crystal/Ceramic oscillation circuit
(2) CR oscillation circuit
(3) External clock input
Fig. 5.4.4.1 OSC3 oscillation circuit