II-132
EPSON
S1C88348/317/316/308 TECHNICAL SOFTWARE
APPENDIX C PROGRAMMING NOTES
Clock Timer
(1) The clock timer is actually made to RUN/STOP
in synchronization with the falling edge of the
256 Hz signal after writing to the TMRUN
register. Consequently, when "0" is written to
the TMRUN, the timer shifts to STOP status
when the counter is incremented "1". The
TMRUN maintains "1" for reading until the
timer actually shifts to STOP status.
Figure C.1 shows the timing chart of the RUN/
STOP control.
Programmable Timer
(1) The programmable timer is actually made to
RUN/STOP in synchronization with the falling
edge of the input clock after writing to the
PRUN0(1) register. Consequently, when "0" is
written to the PRUN0(1), the timer shifts to
STOP status when the counter is decremented
"1". The PRUN0(1) maintains "1" for reading
until the timer actually shifts to STOP status.
Figure C.3 shows the timing chart of the RUN/
STOP control.
Fig. C.1 Timing chart of RUN/STOP control
(2) The SLP instruction is executed when the clock
timer is in the RUN status (TMRUN = "1"). The
clock timer operation will become unstable
when returning from SLEEP status. Therefore,
when shifting to SLEEP status, set the clock
timer to STOP status (TMRUN = "0") prior to
executing the SLP instruction.
Stopwatch Timer
(1) The stopwatch timer is actually made to RUN/
STOP in synchronization with the falling edge
of the 256 Hz signal after writing to the SWRUN
register. Consequently, when "0" is written to
the SWRUN, the timer shifts to STOP status
when the counter is incremented "1". The
SWRUN maintains "1" for reading until the
timer actually shifts to STOP status.
Figure C.2 shows the timing chart of the RUN/
STOP control.
SWRUN(WR)
SWDX
27
28
29
30
31
32
SWRUN(RD)
256 Hz
Fig. C.2 Timing chart of RUN/STOP control
(2) The SLP instruction is executed when the
stopwatch timer is in the RUN status (SWRUN
= "1"). The stopwatch timer operation will
become unstable when returning from SLEEP
status. Therefore, when shifting to SLEEP
status, set the clock timer to STOP status
(SWRUN = "0") prior to executing the SLP
instruction.
Fig. C.3 Timing chart of RUN/STOP control
The event counter mode is excluded from the
above note.
(2) The SLP instruction is executed when the
programmable timer is in the RUN status
(PRUN0(1) = "1"). The programmable timer
operation will become unstable when returning
from SLEEP status. Therefore, when shifting to
SLEEP status, set the clock timer to STOP status
(PRUN0(1) = "0") prior to executing the SLP
instruction.
In the same way, disable the TOUT signal
(PTOUT = "0") to avoid an unstable clock output
to the R27 output port terminal.
(3) Since the TOUT signal is generated asynchro-
nously from the register PTOUT, when the
signal is turned ON or OFF by the register
setting, a hazard of a 1/2 cycle or less is gener-
ated.
(4) When the OSC3 oscillation circuit is made the
clock source, it is necessary to turn the OSC3
oscillation ON, prior to using the programmable
timer.
From the time the OSC3 oscillation circuit is
turning ON until oscillation stabilizes, an
interval of several msec to several 10 msec is
necessary. Consequently, you should allow an
adequate waiting time after turning the OSC3
oscillation circuit ON before starting the count
of the programmable timer. (The oscillation
start time will vary somewhat depending on the
oscillator and on external parts. Refer to the
oscillation start time example indicated in
Chapter 7/Technical Hardware, "ELECTRICAL
CHARACTERISTICS".)
At initial reset, OSC3 oscillation circuit is set to
OFF status.
PRUN0/PRUN1(WR)
PTD0X/PTD1X
42H
41H 40H 3FH 3EH
3DH
PRUN0/PRUN1(RD)
Input clock
TMRUN(WR)
TMDX
57H
58H 59H 5AH 5BH
5CH
TMRUN(RD)
256 Hz