I-64
EPSON
S1C88348/317/316/308 TECHNICAL HARDWARE
5 PERIPHERAL CIRCUITS AND THEIR OPERATION (Output Ports)
5.6.4 DC output
As Figure 5.6.1.1 shows, when "1" is written to the
output port data register, the output terminal
switches to HIGH (VDD) level and when "0" is
written it switches to LOW (VSS) level. When output
is in a high impedance state, the data written to the
data register is output from the terminal at the
instant when output is switched to complementary.
5.6.5 Special output
Besides normal DC output, output ports R25–R27,
R34 and R50 can also be assigned special output
functions in software as shown in Table 5.6.5.1.
Table 5.6.5.1 Special output ports
The frequencies of each signal are changed as shown
in Table 5.6.5.2 according to the drive duty selection.
Table 5.6.5.2 Frequencies of CL and FR signals
s CL and FR output (R25 and R26)
In order for the S1C883xx to handle connection to
an externally expanded LCD driver, output ports
R25 and R26 can be used to output a CL signal
(LCD synchronous signal) and FR signal (LCD
frame signal), respectively.
The configuration of output ports R25 and R26 are
shown in Figure 5.6.5.1.
Register R25D
Register LCCLK
R25 output
CL signal
Register R26D
Register LCFRM
R26 output
FR signal
Fig. 5.6.5.1 Configuration of R25 and R26
The output control for the CL signal is done by the
register LCCLK. When you set "1" for the LCCLK,
the CL signal is output from the output port
terminal R25, when "0" is set, the HIGH (VDD) level
is output. At this time, "1" must always be set for the
data register R25D.
The output control for the FR signal is done by the
register LCFRM. When you set "1" for the LCFRM,
the FR signal is output from the output port terminal
R26, when "0" is set, the HIGH (VDD) level is output.
At this time, "1" must always be set for the data
register R26D.
Since the signals are generated asynchronously
from the registers LCCLK and LCFRM, when the
signals are turned ON or OFF by the register
settings, a hazard of a 1/2 cycle or less is generated.
Figure 5.6.5.2 shows the output waveforms of the
CL and FR signals.
Fig. 5.6.5.2 Output waveforms of CL and FR signals
s TOUT output (R27)
In order for the S1C883xx to provide clock signal to
an external device, the output port terminal R27 can
be used to output a TOUT signal (clock output by
the programmable timer). The configuration of
output port R27 is shown in Figure 5.6.5.3.
Register R27D
Register PTOUT
R27 output
TOUT signal
Fig. 5.6.5.3 Configuration of R27
The output control for the TOUT signal is done by
the register PTOUT. When you set "1" for the
PTOUT, the TOUT signal is output from the output
port terminal R27, when "0" is set, the HIGH (VDD)
level is output. At this time, "1" must always be set
for the data register R27D.
The TOUT signal is the programmable timer
underflow divided by 1/2.
With respect to frequency control, see "5.11 Pro-
grammable Timer".
Since the TOUT signal is generated asynchronously
from the register PTOUT, when the signal is turned
ON or OFF by the register settings, a hazard of a 1/
2 cycle or less is generated.
Figure 5.6.5.4 shows the output waveform of the
TOUT signal.
PTOUT
TOUT output (R27)
01
Fig. 5.6.5.4 Output waveform of TOUT signal
LCCLK/LCFRM
CL output (R25)
FR output (R26)
01
Output port
R25
R26
R27
R34
R50
Special output
CL output
FR output
TOUT output
FOUT output
BZ output
Drive duty
1/32
1/16
1/8
FR signal (Hz)
32
64
CL signal (Hz)
2,048
1,024