S1C88348/317/316/308 TECHNICAL SOFTWARE
EPSON
II-101
17 INTERRUPT (EXCEPTION) PROCESSING
Specifications
Interrupt (exception) processing
Setting of interrupt vector address
(1) main: Interrupt level setting and enables interrupt
Sets an interrupt level (IRQ3–IRQ1) as the below for all interrupts and enables interrupts in the
initialization routine (example for 88316 single chip mode) which is executed by reset exception
processing.
Programmable timer interrupt
IRQ3
Input port interrupt
IRQ3
Serial interface interrupt
IRQ2
Stopwatch timer interrupt
IRQ1
Clock timer interrupt
IRQ1
(2) zero_div:
Zero division exception processing
(3) watchdog: Watchdog timer (NMI) interrupt processing
(4) xxx_intr:
Interrupt processing for peripheral circuit
Notes
(1)
The interrupt level (IRQ3–IRQ1) can be set to adapt to the system.
(2)
Be sure to initialize peripheral circuits which use an interrupt and set interrupt generation condi-
tions beforehand to enable each interrupt.
(3)
Interrupt processing for a peripheral circuit enables all interrupts, and exception processing with
an interrupt vectors is a precondition. Since an interrupt flag is set by the generation of an interrupt
regardless of the interrupt enable register and interrupt flags (I1 and I0), a procedure for polling
interrupt factor flags by software can also be used.
(4)
Since the watchdog timer (NMI) interrupt cannot be masked, be sure to declare the watchdog timer
(NMI) interrupt processing routine and the vector address, regardless of whether or not the
watchdog timer is used.
(5)
To reset the interrupt factor flag, write "1" into the corresponding flags alone, using the AND or LD
instruction. When the OR logic operation instruction has been used, "1" is written for the interrupt
factor flags that have been set to "1" within the same address and those flags are then clear.
(6)
The interrupt flags (I1 and I0) have not been reset in the interrupt processing routine of this
program example, so an interrupt lower than the set level is disabled at the time of generation.
When you wish to accept the next interrupt after an interrupt has been generated, re-setting of the
interrupt flags or resetting the interrupt factor flag is necessary after due consideration for the
nesting level.
(7)
When permitting interrupt nesting, be careful of the stack size.
(8)
Vector addresses for software interrupts can be set up to 109 and to optional address (two bytes
which begin with an even address) from 000026H to 0000FEH.
(9)
The vector addresses 000024H and 000025H cannot be used since this is a system reserved area.
(10) In this program example for interrupt (exception) processing, the vector address setting and
program have been allocated from 000100H for the sake of convenience.
(11) Do not execute the SLP instruction for 2 msec after a NMI interrupt has occurred (when fOSC1 is
32.768 kHz).