I-114
EPSON
S1C88348/317/316/308 TECHNICAL HARDWARE
5 PERIPHERAL CIRCUITS AND THEIR OPERATION (Programmable Timer)
CHSEL: 00FF30HD3
Selects the channel of the TOUT signal.
When "1" is written: Timer 0 underflow
When "0" is written: Timer 1 underflow
Reading:
Valid
Select whether the timer 0 underflow will be used
for the TOUT signal or the timer 1 underflow will
be used. When "0" is written to CHSEL, timer 0 is
selected and when "1" is written, timer 1 is selected.
When the 16-bit mode has been selected, it is fixed
to timer 1 (underflow of the 16-bit timer), and
setting of CHSEL becomes invalid.
At initial reset, CHSEL is set to "0" (timer 1
underflow).
PTOUT: 00FF30HD2
Controls the TOUT signal output.
When "1" is written: TOUT signal output
When "0" is written: HIGH level (DC) output
Reading:
Valid
PTOUT is the output control register for TOUT
signal. When "1" is set, the TOUT signal is output
from the output port terminal R27 and when "0" is
set, HIGH (VDD) level is output. At this time, "1"
must always be set for the data register R27D.
At initial reset, PTOUT is set to "0" (HIGH level
output).
PPT0, PPT1: 00FF21HD2, D3
Sets the priority level of the programmable timer
interrupt.
The two bits PPT0 and PPT1 are the interrupt
priority register corresponding to the programma-
ble timer interrupt. Table 5.11.10.3 shows the
interrupt priority level which can be set by this
register.
Table 5.11.10.3 Interrupt priority level settings
At initial reset, this register is set to "0" (level 0).
EPT0, EPT1: 00FF23HD6, D7
Enables or disables the generation of an interrupt
for the CPU.
When "1" is written: Interrupt enabled
When "0" is written: Interrupt disabled
Reading:
Valid
The EPT0 and EPT1 are interrupt enable registers
that respectively correspond to the interrupt factors
for timer 0 and timer 1. Interrupts set to "1" are
enabled and interrupts set to "0" are disabled.
When the 16-bit mode is selected, setting of EPT0
becomes invalid.
At initial reset, this register is set to "0" (interrupt
disabled).
FPT0, FPT1: 00FF25HD6, D7
Indicates the programmable timer interrupt
generation status.
When "1" is read:
Interrupt factor present
When "0" is read:
Interrupt factor not present
When "1" is written: Resets factor flag
When "0" is written: Invalid
The FPT0 and FPT1 are interrupt factor flags that
respectively correspond to the interrupts for timer 0
and timer 1 and are set to "1" in synchronization
with the underflow of each counter.
When set in this manner, if the corresponding
interrupt enable register is set to "1" and the
corresponding interrupt priority register is set to a
higher level than the setting of interrupt flags (I0
and I1), an interrupt will be generated to the CPU.
Regardless of the interrupt enable register and
interrupt priority register settings, the interrupt
factor flag will be set to "1" by the occurrence of an
interrupt generation condition.
To accept the subsequent interrupt after interrupt
generation, re-setting of the interrupt flags (set
interrupt flag to lower level than the level indicated
by the interrupt priority registers, or execute the
RETE instruction) and interrupt factor flag reset are
necessary. The interrupt factor flag is reset to "0" by
writing "1".
When the 16-bit mode is selected, the interrupt
factor flag FPT0 is not set to "1" and a timer 0
interrupt cannot be generated. (In the 16-bit mode,
the interrupt factor flag FPT1 is set to "1" by an
underflow of the 16-bit counter.)
At initial reset, this flag is reset to "0".
PPT1
PPT0
Interrupt priority level
1
0
1
0
1
0
Level 3 (IRQ3)
Level 2 (IRQ2)
Level 1 (IRQ1)
Level 0 (None)