I-106
EPSON
S1C88348/317/316/308 TECHNICAL HARDWARE
5 PERIPHERAL CIRCUITS AND THEIR OPERATION (Programmable Timer)
5.11.5 Event counter mode
Timer 0 includes an even counter function that
counts by inputting an external clock (EVIN) to
input port K10. This function is selected by writing
"1" to the timer 0 counter mode selection register
EVCNT.
When the event counter mode is selected, timer 0
operates as an event counter and timer 1 operates
as a normal timer in 8-bit mode. In the 16-bit mode,
timer 0 and timer 1 operate as 1 channel 16-bit
event counter. In the event counter mode, since the
timer 0 is clocked externally, the settings of regis-
ters PSC00/PSC01 become invalid.
Count down timing can be controlled by either the
falling edge or rising edge selected by the timer 0
pulse polarity selection register PLPOL. When "0" is
written to the register PLPOL, the falling edge is
selected, and when "1" is written, the rising edge is
selected. The timing is shown in Figure 5.11.5.1.
For a reliable count when "with noise rejecter" is
selected, you must allow 0.98 msec or more pulse
width for both LOW and HIGH levels. (The noise
rejecter allows clocking counter at the second
falling edge of the internal 2,048 Hz signal after
changing the input level of the K10 input port
terminal. Consequently, the pulse width that can
reliably be rejected is 0.48 msec.)
Figure 5.11.5.2 shows the count down timing with
the noise rejecter selected.
Input clock
to counter
Count data
n
n-1
n-2
n-3
EVIN input (K10)
2,048 Hz
When "0" is set into register PLPOL.
Fig. 5.11.5.2 Count down timing with noise rejecter
The event counter mode is the same as the timer
mode except that the clock is external (EVIN).
See "5.11.2 Count operation and setting basic mode"
for the basic operation and control.
5.11.6 Pulse width measurement timer mode
Timer 0 includes a pulse width measurement function
that measures the width of the input signal to the K10
input port terminal. This function is selected by
writing "1" to the timer function selection register
FCSEL when in the timer mode (EVCNT = "0").
When the pulse width measurement mode is
selected, timer 0 operates as an pulse width measure-
ment and timer 1 operates as a normal timer in 8-bit
mode. In the 16-bit mode, timer 0 and timer 1 operate
as 1 channel 16-bit pulse width measurement.
The level of the input signal (EVIN) for measure-
ment can be changed either a LOW or HIGH level
by the timer 0 pulse polarity selection register
PLPOL. When "0" is written to register PLPOL, a
LOW level width is measured and when "1" is
written, a HIGH level width is measured. The
timing is shown in Figure 5.11.6.1.
EVIN input (K10)
Count data
n
n-1
n-2
n-3
n-4
n-5
n-6
PLPOL
EVCNT
01
1
PRUN0
Fig. 5.11.5.1 Timing chart for event counter mode
The event counter also includes a noise rejecter to
eliminate noise such as chattering for the external
clock (EVIN). This function is selected by writing
"1" to the timer 0 function selection register FCSEL.
EVIN input (K10)
Count data
PLPOL
Prescaler
output clock
n
n-1
n-2
n-3
n-4
Input clock
to timer
PRUN0
FCSEL
n-5
n-6
n-7
n-8
Fig. 5.11.6.1 Timing chart for pulse width measurement timer mode