II-38
EPSON
S1C88348/317/316/308 TECHNICAL SOFTWARE
8 SERIAL INTERFACE 1 (CLOCK SYNCHRONOUS INTERFACE)
Clock synchronous serial interface
external
osc1toosc3,osc3toosc1
external
vdd_ngf
public
sio_init,siorv,siotr,siorv_intr,siotr_intr
public
receive_buffer,trans_buffer,receive_flag,trans_flag
;
siorv_vector
equ
000012h
;sio receive interrupt vector offset
siotr_vector
equ
000014h
;sio trans interrupt vector offset
sio
equ
003000h
;program start address offset
br_io
equ
0ffh
;base reg. address (set i/o area)
mode
equ
00ff02h
;mode control reg.
ioc1
equ
00ff61h
;p1x i/o control reg.
p1d
equ
00ff63h
;p1x port data
smd
equ
00ff48h
;serial interface mode set reg.
ser
equ
00ff49h
;serial interface error and trriger reg
trxd
equ
00ff4ah
;trans/recive data reg.
intr_pr0
equ
00ff20h
;interrupt priority reg. 0
intr_en1
equ
00ff23h
;interrupt enable reg. 1
intr_fac1
equ
00ff25h
;interrupt factor reg. 1
;
data
receive_buffer:db
[256]
;sio receive bufffer
trans_buffer:
db
[256]
;sio trans buffer
receive_flag:
db
[1]
;trans complete flag
trans_flag:
db
[1]
;receive complete flag
code
Vector address setting for serial interface interrupt
intr_vectors:
;
org
intr_vectors+siorv_vector
dw
siorv_intr
;sio receive interrupt
;
org
intr_vectors+siotr_vector
dw
siotr_intr
;sio trans interrupt
;
(1) Initialization for clock synchronous serial interface (master mode)
org
intr_vectors+sio
;************************************************************************
;*
*
;*
sio master mode initialize (p13=slave ready)
*
;*
*
;************************************************************************
;*** initialize routine
sio_init:
;p17-14=programmable output,p13=slave ready,p12-10=sio terminal
ld
br,#br_io
;set br reg. address to 0ffxxh
ld
[br:low p1d],#11110110b
;/sclk="h",sout="h"
ld
[br:low ioc1],#11110110b
ld
[br:low ser],#01110000b
;rxen=dis.txen=dis.
;serial mode:no-parity,clock=fosc3/4,sio master mode and serial i/o select
ld
[br:low smd],#00010001b
;set serial interface mode
ld
a,[br:low intr_pr0]
;interrupt priority reg.
and
a,#11001111b
or
a,#00100000b
ld
[br:low intr_pr0],a
;set psif1,0 to /irq2
ld
a,[br:low intr_en1]
and
a,#01111000b
or
a,#00000011b
ld
[br:low intr_en1],a
;esrec and estra intr. en.
ld
a,sc
and
a,#00111111b
or
a,#01000000b
ld
sc,a
;i1 flag clear (en. /irq2 intr.)
ret
Source List
(1)